Author Topic: TE0706-03 Dual Ethernet  (Read 818 times)

bigguiness

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TE0706-03 Dual Ethernet
« on: September 14, 2020, 08:03:12 PM »
Hello all,

Is there a default design for the TE0720 / TE0706-03 that has both Ethernet ports working?

If not does anyone know what needs to be done?

Thanks

JH

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Re: TE0706-03 Dual Ethernet
« Reply #1 on: September 15, 2020, 06:42:12 AM »
Hi,
there is an older 16.2 design which works fine:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/Reference_Design/2016.2/carrier_te0706_eth
--> you can test with  prebuilt binaries

I've start start 19.2 update but unfortunately it doesn't work complete at the moment and I doesn't figured out the reason until now (ETH0 works, but on ETH1 only link up). Unfortunately I can't get to work on it right now.

br
John

JH

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Re: TE0706-03 Dual Ethernet
« Reply #2 on: December 02, 2020, 12:13:13 PM »
Hi,

I'm not sure if you need still this information, but I got both ETH running on TE0706 with TE0720 and Vivado 19.2. There was only GMII2RGMII driver missing on petalinux kernel.

You can download the project from:

    https://nextcloud.trenz-electronic.de/index.php/s/NsJB6Y2beFaY5ca

It includes only prebuilt image.ub for 1GB DDR and boot.bin for 1cf version of the module.

I will put it online during the next week with all assembly variants.

Best regards

John

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #3 on: December 02, 2020, 05:19:03 PM »
Hi John,

Yes, I do still need this. Thanks.

Question... How do i get this loaded on my TE0720?

I'm still trying to figure out how the Vivado/Vitis/Petalinux stuff all works. Unfortunately I have 2020.1 installed not 19.2 (2019.2?). But, I assume I can still load the prebuilt images on the TE0720 using the 2020.1 tools. Correct?

Will you be putting the full design online? For my end product I need both Ethernet ports to work and a starting point would really be helpful.

Thanks

JH

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Re: TE0706-03 Dual Ethernet
« Reply #4 on: December 17, 2020, 06:50:33 AM »
Hi,
simple way is to boot from SD. Put Boot.bin and image.ub on the SD Card (fat32 partition)
PS: Documentation is also online now:
https://wiki.trenz-electronic.de/display/PD/TE0720+ETH0706

In case you want to programm QSPI flash, this should work also with 20.1 and 19.2 binaries
PS: Here are some notes for QSPI programming with different vivado versions: https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937

br
John

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #5 on: January 04, 2021, 07:06:11 PM »
Hi John,

I'm going to try the prebuilt image in order to test the second ethernet port with my TE0720-03-1CFA board and the TE0706 carrier. BTW, is there any way to verify that my TE0720 is actually that variant?

Is there any possibility of getting the design updated to the 2020.2 tools? That's the latest available from Xilinx and seems to be the most "stable" version I have tried.

Thanks,
Hartley

JH

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Re: TE0706-03 Dual Ethernet
« Reply #6 on: January 06, 2021, 08:30:10 AM »
Hi,
Quote
BTW, is there any way to verify that my TE0720 is actually that variant?
You can send me the serial number of your module (number on small white sticker with QR code) and I will check which variant you has.

Quote
Is there any possibility of getting the design updated to the 2020.2 tools? That's the latest available from Xilinx and seems to be the most "stable" version I have tried.

It first I must get our basic workflow running again with 20.2 --> Xilinx has made some changes again. I found problems with Vitis scripts and with petalinux.
Vitis scripts problems are mostly solved.
On petalinux I've problems to export kernel and uboot changes (petalinux-config -c kernel or petalinux-config -c u-boot) from yocto developer space to the user layer with custom receipts. On older version this was possible with "petalinux-build -c kernel -x finish -f" and  "petalinux-build -c u-boot -x finish -f", now this not longer works. When you say 20.2 is most "stable" version, do you know a solution for this problem?

But updating this Dual ETH example design will take a little longer, because I most do at first the primary designs for mostly all our boards.

But you can do following.
1. Create 2019.2 design with 2019.2 and open again with 2020.2 and use Xilinx IP update function to update all Xilinx IPs to 2020.2.
 --> in case you has only 20.2 installed, start _create_win_setup.cmd and select min. setup, scripts will copy design_basic_settings.cmd in the basefolder of the reference design
--> open "design_basic_settings.cmd" with notpadd++ and change vivado version from 2019.2 to 2020.2.
-->run start _create_win_setup.cmd again and follow instruction.
--> PS: with new 20.2 design I will make it easer to create it directly with other vivado version
2 Generate Bistream and export XSA
3 create petalinux project from scratch, for changes which must be done, see our wiki documentation of the dual eth. But do this you must also find a solution for my problem with receipe export on 20.2(or you generate these layer receipts manually)

br
John
Cr



bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #7 on: January 07, 2021, 05:25:38 PM »
Hi John,

The serial number on my board is 486501.

The prebuilt image does work on my board. I did a quick test of both Ethernet ports and they seem to work fine. I did notice that the two LEDs on each jack don't seem to indicate anything. I was expecting the normal "activity" and "link" status to be indicated by them but they seem to be static.

By 2020.2 being "stable" I mean it actually works...

I tried many different Ubuntu VM setups with different Vivado version and had problem with the VM either being reeallyyy slow or just plan hanging when Vivado was running. I also had a lot of problems just getting the USB/JTAG connection working.

I finally just bought a NUC and installed Ubuntu directly on it (no VM). With that and Vivado 2020.2 I have not had any of those issues.

I am still pretty new to this whole FPGA stuff so a lot of my problems may just be a learning curve...

I'm getting a pretty good idea on how Vivado works and am a bit more comfortable with Vitis but the whole petalinux thing is still really confusing. I'm a lot more familiar with the Buildroot process and Yokco just doesn't make sense. For instance, how do you modify/change what is in the rootfs? How do you change the kernel config? How do you add a custom driver module to the kernel? How do you add a custom application to the build and rootfs? And then how do you modify the boot so that the custom application is ran automatically?

I'm sure a lot of these questions have answers on the web but it's really difficult to find anything other than "just run this script and everything works". And if you do "run the script" you find out if doesn't actually work... It's a a bit frustrating.

Thanks for all your help,
Hartley

JH

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Re: TE0706-03 Dual Ethernet
« Reply #8 on: January 08, 2021, 01:26:33 PM »
Hi,

petalinux is yocto based. to work with VM you must configure more powerful VM.
I've make some notes for 2020.2 with minimum requirements for vm and need packages:
https://wiki.trenz-electronic.de/display/PD/PetaLinux
for older versions see:
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart


PS: 486501 is TE0720-03-1CF

br
John

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #9 on: January 08, 2021, 07:42:43 PM »
Hi John,

Thanks for verifying my TE0720 version.

I had my VM setup similar to your minimum requirements notes, just with a larger partition size. But the performance was really bad, this could be due to my laptop only being a 7th Gen Core i7.

The NUC I'm using now has a 10th Gen Core i7. With that, as well as 64GB and not running as a VM, it's a lot better.

I have noticed that the Vivado editor is terrible and the realtime syntax checker kills performance with larger source files. But that's another issue.....

Thanks,
Hartley

JH

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Re: TE0706-03 Dual Ethernet
« Reply #10 on: January 08, 2021, 11:13:09 PM »
Hi,
Yes petalinux need many resource.
I think sooner or later we Xilinx also Vivado only under linux fully supported. Also the AI flow of Vitis goes only under linux

On my PC I've spend my VM much more RAM, this helps also.

Regarding Editor, I use notpad++ I can work best with this. You can also specify third party editor under vivado:
Tools -->settings --> Text Editor

br
John

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #11 on: February 17, 2021, 08:59:17 PM »
Hi John,

Any update on if/when a 2020.2 BSP might be available for the TE0720 (and possibly the dual ethernet support)?

Thanks,
Hartley

JH

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Re: TE0706-03 Dual Ethernet
« Reply #12 on: February 18, 2021, 01:24:15 PM »
Hi,
20.2 test board design is online now:
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board
but this is with single ETH only.

when you add 2019.2 configuration from https://wiki.trenz-electronic.de/display/PD/TE0720+ETH0706
 to the 2020.2 manually (block design, constrains, linux), I think you can get second eth also running.

br
John

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #13 on: April 05, 2021, 06:07:45 PM »
Hi John,

I'm finally at the point that I need to dig into creating the Vivado design for the dual-ethernet. Hopefully I will figure it out this week.

Also, I have been working on the carrier board design/layout I will need for our product. I started with the TE0703-05 carrier design since I need two ethernet ports. I have a couple questions.

1) Is the 125MHz output clock from the ethernet on the TE0703 a general purpose input clock to the Zynq PL or is it actually needed for the second ethernet?

2) Do I need to, or should I, be supplying a clock to the PL for by design? What clocks are actually available to the PL from the TE0720?

3) What's up with the various PL bank pins that are tied together on the TE0720? None of these connections leave the board but I want to make sure I don't need to do something special in Vivado to deal with them. Bank33 has a number of these and Bank35 has one.

Thanks for your help,
Hartley

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #14 on: April 06, 2021, 01:05:22 AM »
Hi John,

Any possibility of the TE0720+ETH0706 design getting updated to 2020.2?

I tried installing 2019.2 on my Windows laptop with 2020.2 already installed. Now it looks like the 2020.2 install is a bit hosed.

I'm actually doing all my Xilinx stuff on a NUC that is running Ubuntu and I really don't want to screw up that setup!

Thanks,
Hartley

bigguiness

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Re: TE0706-03 Dual Ethernet
« Reply #15 on: April 06, 2021, 07:39:34 PM »
Hi John,

I'm trying to add the 2019.2 configuration from https://wiki.trenz-electronic.de/display/PD/TE0720+ETH0706
to the 2020.2 test board design https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board

I _think_ I got all the block design, constrains, and linux differences but when I try to run the _create_linux_setup.sh
Vivado fails to build the design. Following is the Tcl Console output:

---

Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/bigguiness/zynq/te0720-eth706/constraints/_i_TE0720-SC.xdc
 /home/bigguiness/zynq/te0720-eth706/constraints/_i_bitgen_common.xdc
 /home/bigguiness/zynq/te0720-eth706/constraints/_i_eth1.xdc
 /home/bigguiness/zynq/te0720-eth706/constraints/_i_common.xdc
 /home/bigguiness/zynq/te0720-eth706/constraints/vivado_target.xdc
  ------
Set processing order normal for /home/bigguiness/zynq/te0720-eth706/constraints/_i_TE0720-SC.xdc
Set use for implementation only for /home/bigguiness/zynq/te0720-eth706/constraints/_i_TE0720-SC.xdc
Set processing order normal for /home/bigguiness/zynq/te0720-eth706/constraints/_i_bitgen_common.xdc
Set use for implementation only for /home/bigguiness/zynq/te0720-eth706/constraints/_i_bitgen_common.xdc
Set processing order normal for /home/bigguiness/zynq/te0720-eth706/constraints/_i_eth1.xdc
Set use for implementation only for /home/bigguiness/zynq/te0720-eth706/constraints/_i_eth1.xdc
Set processing order normal for /home/bigguiness/zynq/te0720-eth706/constraints/_i_common.xdc
Set use for implementation only for /home/bigguiness/zynq/te0720-eth706/constraints/_i_common.xdc
Set processing order normal for /home/bigguiness/zynq/te0720-eth706/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/bigguiness/zynq/te0720-eth706/constraints/vivado_target.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   /home/bigguiness/zynq/te0720-eth706/block_design/zsys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zsys_bd
  TE::PR_TOPLEVELNAME: zsys_wrapper
  ------
  TE::IS_ZSYS:         true
INFO: [TE_UTIL-2] Following block designs were found:
   /home/bigguiness/zynq/te0720-eth706/block_design/zsys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0720_1q:part0:1.0, FPGA: xa7z020clg484-1q at 2021-01-08T07:45:53.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD::TCL 103-2003] Currently there is no design <zsys> in project, so creating one...
Wrote  : </home/bigguiness/zynq/te0720-eth706/vivado/te0720-eth706.srcs/sources_1/bd/zsys/zsys.bd>
INFO: [BD::TCL 103-2004] Making design <zsys> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "zsys".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog: 
trenz.biz:user:SC0720:* xilinx.com:ip:gmii_to_rgmii:* trenz.biz:user:labtools_fmeter:* xilinx.com:ip:proc_sys_reset:* xilinx.com:ip:processing_system7:* xilinx.com:ip:util_vector_logic:* xilinx.com:ip:vio:* xilinx.com:ip:xlconcat:* xilinx.com:ip:xlconstant:*  .
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins processing_system7_0/GMII_ETHERNET_1'
ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: .
ERROR: (TE_INIT-146) Script (TE::VIV::import_design) failed: .
ERROR:(TE) Script (TE::INIT::run_board_selection) failed: .
ERROR:(TE) Script (TE::main) failed: .
update_compile_order -fileset sources_1

---

All the pieces appear to be in the block design they are just not hooked up. Also, the ZYNQ7
Processing System is missing a number of the ports. Specifically the GMI_ETHERNET_1 that
is causing the error.

Is there something different needed in the 2020.2 zsys_bd.tcl file vs. the 2019.2 file to enable
that port and the others needed?

Thanks,
Hartley

JH

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Re: TE0706-03 Dual Ethernet
« Reply #16 on: April 12, 2021, 07:24:53 AM »
Hi,
create the project with 19.2 and reopen with 20.2.
alternatively change manually"@set VIVADO_VERSION=2019.2" to "@set VIVADO_VERSION=2020.2" in "design_basic_settings.cmd"  and run "_create_linux_setup.sh" again from the ETH0706 project.

If it works depends on changes from Xilinx IPs.

PS: Linux part must be done completely again manually (you can't use our petalinux template project in 2020.2). And Xilinx has changed a lot of things in 2020.2 petalinux, so it can happens that you must done much more to get it running in 2020.2

br
John