TE0802 problems with application acceleration platform in vitis 2019.2

[ycalderon]

Hello.

We are creating a vitis 2019.2 platform for application acceleration in te0802.

We followed for the most part Xilinx documentation (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1393-vitis-application-acceleration.pdf page 506 onwards).

We start by creating a vivado project using te0802 board files. When adding the Clocking wizard IP we see the following message:

Code Select Expand

startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
create_bd_cell: Time (s): cpu = 00:01:15 ; elapsed = 00:01:55 . Memory (MB): peak = 8739.797 ; gain = 839.617 ; free physical = 2642 ; free virtual = 7049
endgroup


Despise this error we manage to create the XSA file and build the petalinux 2019.2 project.

We created and build the platform in Vitis and manage to compile the vector addition example using it.

TE0802 boots correctly. We set the XRT environment and run the example. TE0802 then hangs.

Code Select Expand


root@te0802_min:~# ./vadd.exe binary_container_1.xclbin
[  143.434121] [drm] Pid 2259 opened device
[  143.438095] [drm] Pid 2259 closed device
[  143.452891] [drm] Pid 2259 opened device
Loading: 'binary_container_1.xclbin'
[  143.721627] [drm] Finding IP_LAYOUT section header
[  143.721645] [drm] Section IP_LAYOUT details:
[  143.726542] [drm]   offset = 0x54fcf0
[  143.730815] [drm]   size = 0x58
[  143.734702] [drm] Finding DEBUG_IP_LAYOUT section header
[  143.737826] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[  143.743133] [drm] Finding CONNECTIVITY section header
[  143.749050] [drm] Section CONNECTIVITY details:
[  143.754099] [drm]   offset = 0x54fd48
[  143.758620] [drm]   size = 0x28
[  143.762308] [drm] Finding MEM_TOPOLOGY section header
[  143.765437] [drm] Section MEM_TOPOLOGY details:
[  143.770478] [drm]   offset = 0x54fbf8
[  143.774998] [drm]   size = 0xf8
[  143.779783] [drm] No ERT scheduler on MPSoC, using KDS


Using GDB we manage to confirm that the error happens when submitting the execution command buffer using EXECBUF ioctl. According to XRT execution flow (https://xilinx.github.io/XRT/2019.2/html/execution-model.html), te0802 hangs between steps 6 and 7.
   
Any help or input on the issue will be greatly appreciated.

Cheers.

[ycalderon]

Some extra info:

1. xbutil query

Code Select Expand

  root@te0802_min:~# xbutil query
   INFO: Found total 1 card(s), 1 are usable
   ~~~~~~~~~~~~~~~~~~~~~~~~~[ 1626.797235] [drm] Pid 2376 opened device
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   System Configuration
   OS name:        Linux[ 1626.809147] [drm] Pid 2376 closed device
   
   Release:        4.19.0-xilinx-v2019.2
   Version:        #1 SMP Fri Aug 7 09:04:28 UTC 2020
   Machine:        aarch64
   Glibc:          2.28
   Distribution:   N/A
   Now:            Wed Aug 12 10:24:10 2020
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   XRT Information
   Version:        2.3.0
   Git Hash:       7e3540d2707443d8c824669ef4272b33ce2f9ba4
   Git Branch:     2019.2
   Build Date:     2019-10-22 07:31:35
   ZOCL:           2018.2.1
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   Shell                           FPGA                            IDCode
   te0802_min                      N/A                             N/A
   Vendor          Device          SubDevice       SubVendor
   0x10ee          N/A             N/A             N/A
   DDR size        DDR count       Clock0          Clock1          Clock2
   4 GB            1               100             0               0
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   Memory Status
        Tag         Type        Temp(C)  Size    Mem Usage       BO count
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   Streams
        Tag         Flow ID  Route ID Status   Total (B/#)     Pending (B/#)
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   Xclbin UUID
   0
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   Compute Unit Status
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   INFO: xbutil query succeeded.

2. xbutil scan

   

Code Select Expand


   root@te0802_min:~# xbutil scan
   INFO: Found total 1 card(s), 1 are usable
   ~~~~~~~~~~~~~~~~~~~~~~~~~[ 1758.861321] [drm] Pid 2386 opened device
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   System Co[ 1758.870924] [drm] Pid 2386 closed device
   nfiguration
   OS name:        Linux
   Release:        4.19.0-xilinx-v2019.2
   Version:        #1 SMP Fri Aug 7 09:04:28 UTC 2020
   Machine:        aarch64
   Glibc:          2.28
   Distribution:   N/A
   Now:            Wed Aug 12 10:26:22 2020
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   XRT Information
   Version:        2.3.0
   Git Hash:       7e3540d2707443d8c824669ef4272b33ce2f9ba4
   Git Branch:     2019.2
   Build Date:     2019-10-22 07:31:35
   ZOCL:           2018.2.1
    [0]:te0802_min


I cannot put the output of dmesg because of post character limit.

[JH]

Hi,

Code: [Select]

startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
create_bd_cell: Time (s): cpu = 00:01:15 ; elapsed = 00:01:55 . Memory (MB): peak = 8739.797 ; gain = 839.617 ; free physical = 2642 ; free virtual = 7049
endgroup

Despise this error we manage to create the XSA file and build the petalinux 2019.2 project.

This isn't a error.  We didn't provide any board automation for a MMCM, so you must setup manually (connect clk and configure IP).


As I know Xilinx acceleration needs special preparation of the vivado project, default XSA export will not work, but I haven't any experience until now, so I can't help much.

Here are some links which maybe helps:
https://www.xilinx.com/html_docs/xilinx2019_1/sdsoc_doc/oar1554997070123.html
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1209-embedded-design-tutorial.pdf
https://www.hackster.io/news/microzed-chronicles-vitis-acceleration-creating-a-vm-setup-363946fb4ede
https://www.hackster.io/news/microzed-chronicles-vitis-sw-platform-fd3921137bcf

br

John