TE0720 Reference Design 2020.1

[vishav26]

Dear Trenz Electronics,

I have been using TE0720 board for an year now. The idea is that we want to boot yocto linux 3.0 (zeus) on the board which is currently supported in Petalinux 2020.1. The latest version of Reference Design I could find https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/Reference_Design was 2019.2. I followed the setup https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-SoftwareDesign-PetaLinux which worked great with Petalinux 2019.2.

But since I am seeking yocto linux 3.0 (zeus), I tried to do the same setup with petalinux 2020.1 which gave me some errors. If you understand the problem, I have following questions:

1.   Is there any plan to update the reference design to 2020.1. If yes, may I know when can we expect it?
2.   If not, are there any instructions that you could suggest me to use the reference design with petalinux 2020.1?

Thanks & Regards
Vishav

[JH]

Hi,

1.   Is there any plan to update the reference design to 2020.1. If yes, may I know when can we expect it?

I didn't decide until now if we skip 20.1 or not. but in case we start tu update 20.1 we will not start before august.

If not, are there any instructions that you could suggest me to use the reference design with petalinux 2020.1?

Option 1: In case you has also 19.2 installed:

   
• create Vivado project with 19.2 and close it
• open project again with 20.1 and update IPs
• generate bitstream and export XSA
• create new petalinux project with 20.1 petalinux and add our changes manually :https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-SoftwareDesign-PetaLinux
• Maybe you must also generate a new 20.1 Xilinx default fsbl and add our changes (depends on changes from Xilinx on the FSBL)

19.2 design allows also to generate the project directly with 20.1.

   
• (this is need only if 19.2 is also installed) start "_create_win_setup.cmd" and use option 1(Create minimum setup of CMD-Files and exit Batch)
• (this is need only if 19.2 is also installed)  open generated "design_basic_settings.cmd" with text editor and change default Vivado version from 19.2 to 20.1 and save
• start "_create_win_setup.cmd" and use option 0(Module selection guide, project creation...prebuilt export...)
• follow instruction and agree that you open it with wrong vivado version (not tested, so it can happens that not all things works)
• generate bitstream and export XSA
• create new petalinux project with 20.1 petalinux and add our changes manually :https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-SoftwareDesign-PetaLinux
• Maybe you must also generate a new 20.1 Xilinx default fsbl and add our changes (depends on changes from Xilinx on the FSBL)

brJohn

[vishav26]

Hi,

Thank you for your reply. I tried the steps you mentioned in the post. Here is the sequence of what I did.

1. I opened the .xpr file from vivado folder in vivado2020.1 and re generated the bitstream. I exported the xsa file.
2. I created a petalinux2020.1 project with zynq template and using the xsa file generated in step1 called the command

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petalinux-config --get-hw-description
3. Then I called the following commands

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petalinux-config   

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petalinux-config -c u-boot

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petalinux-config -c kernel

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petalinux-config -c rootfs
Note: If I don't call these commands and directly change the config files as in step 4. Then I get compilation errors.
4. I did the changes manually as stated in

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https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-SoftwareDesign-PetaLinux
5. Run

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petalinux-build
6. After build I get the u-boot.elf and also zynq-fsbl.elf
7. I created a BOOT.bin file using .bif file containing new u-boot and fsbl
8. While flashing I get the error "Problem in running uboot"
9. Tried an alternative. Used the fsbl from Trenz and the new uboot. The flash is sucessful but nothing happens on reboot.

I am not sure if I did everything as you suggested. If I missed something, please let me know. Any support would be appreciated.

Thanks & Regards
Vishav

[JH]

Hi,
which carrier did you use? you can also boot direclty from SD (put Boot.bin and image.ub  to SD(one fat32 partition ) and set boot mode to SD).
Did you select design for your assembly variant? Did the prebuilt Boot.bin boot?.

2. I created a petalinux2020.1 project with zynq template and using the xsa file generated in step1 called the command

--> you mean you has use our petalinux template or did you create a new project (petalinux-create --type project --template zynq --name <PROJECT_NAME>)?
--> you must create new project and setup everything automatically.

I would suggest to test at first baremetal hello world, if this works you can switch to linux. --> you can use the same FSBL and in this case you can better narrow down the reason for the issue. You can alsoi enable debug flags for FSBL to see where FSBL has a problem, in case you see nothing on the uart console

Tried an alternative. Used the fsbl from Trenz and the new uboot. The flash is sucessful but nothing happens on reboot.

which one did you use?
We provide 2 fsbl, one normal fsbl (with some addition features --> we create it with Vitis, not petalinux . FSBL sourcecode is included in the download. Petalinux use defautl ine). and the second FSBL for flash progamming.

Some note: With 2019.x and 2020.1 flash programming depends also on the QSPI Flash content. It's a new feature (or bug) from vivado. Here some summery for QSPI Flash programming:

Possible cases and solutions:
Vivado 2017.2 and older
    Case1: flash is empty
        no issue
    Case 2: flash contains bootable design:
        Possible Problem 1: running OS on zynq can prevent vivado to get access to QSPI
            Solution 1: Stop booting for example on uboot console and try again
            Solution 2: change boot mode some other a mode which does not boot any design


Vivado 2017.3 up to 2018.3
Programming procedure has changed (XIlinx AR#70146), user must add additional FSBL now which initialise PS before Xilinx micro Uboot starts

    Case 1: flash is empty
        Problem 1: Default FSBL stops working with error stage,because it didn't find bootable image on flash.
            Solution 1: used special FSBL where boot mode is set fix to JTAG, see Xilinx AR#70548
    Case 2: flash contains bootable design
        mostly no issue, default FSBL or special FSBL can be used to program flash
        Possible Problem 1: running OS zynq can prevent vivado to get access to QSPI
            Solution 1: Stop booting for example on uboot console and try again
            Solution 2: change boot mode some other mode which


Vivado 2019.x or newer (last tested version 2020.1)
Same programming procedure like 2017.3 up to 2018.3, but Vivado access to Zynq seems to be changed.

    Case 1: flash is empty
        Problem 1: Default FSBL stops working with error stage,because it didn't find bootable image on flash.
            Solution: used special FSBL where boot mode is set fix to JTAG, see Xilinx AR#70548
    Case 2: flash contains bootable design
        Problem 1:  Vivado starts design from QSPI Flash before selected FSBL will be programmed. This seems to prevent Vivado from starting the selected FSBL correctly, which leads to inconsistencies and terminates the programming
            Solution 1: use the same FSBL which was used on the design which was programmed
            Solution 2: change boot mode some other a mode which does not boot any design and use special FSBL
        Possible Problem 2: running OS zynq can prevent vivado to get access to QSPI
            Solution 1: Stop booting for example on uboot console and try again
            Solution 2: change boot mode some other a mode which does not boot any design

br
John

[vishav26]

Hi,

Thanks for the reply. Here are my answers.

which carrier did you use? you can also boot direclty from SD (put Boot.bin and image.ub  to SD(one fat32 partition ) and set boot mode to SD).

I am using Xilinx Platform Cable to flash the image.

Did you select design for your assembly variant? Did the prebuilt Boot.bin boot?

Yes, I selected 1cf_1gb as variant. The prebuilt BOOT.bin which comes by default from trenz package booted successfully. But the BOOT.bin which I created using petalinux2020.1 linux images does not boot. While flashing it says "Problem in running u-boot"

you mean you has use our petalinux template or did you create a new project (petalinux-create --type project --template zynq --name <PROJECT_NAME>)?

I tried to create same template (one from trenz) in petalinux2020.1 but got error when I run

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petalinux-config --get-hw-description The error says Error: Failed to create workspace directory
Therefore I created the project using zynq template and did the changes manually.

I would suggest to test at first baremetal hello world, if this works you can switch to linux

I tried running hello world. With the default fsbl (the one comes in prebuilt) hello world works. With the new fsbl (using vitis 2020.1 and using source code from Trenz), the error is problem in running u-boot. I also created flash_fsbl (using vitis 2020.1 and using source code from Trenz) but it doesn't help too.

Strange thing was that I compiled an fsbl using vitis 2019.2 and source code from trenz and use this for booting hello application. I got the same error as in 2020.1. The procedure I followed was:
1. Open Vitis 2019.2
2. Create new application. Use test_board_1cf_1gb.xsa file from trenz
3. Select project template as zynq Fsbl
4. Replace the source files with the one offered by trenz
5. Compile the project and obtain fsbl.elf files
6. Use this fsbl.elf file to flash hello application.

which one did you use?
We provide 2 fsbl, one normal fsbl (with some addition features --> we create it with Vitis, not petalinux . FSBL sourcecode is included in the download. Petalinux use defautl ine). and the second FSBL for flash progamming.

I tried using both but same results. Problem in running u-boot

Other things that I have tried:
1. Run Configurations: Instead of flashing u-boot on flash, I run it directly on RAM. While the default u-boot application works as expected, the new u-boot gives the error Cannot halt processor core, timeout

My assumption:
1. Both fsbl and u-boot files from petalinux2020.1 have problems. This can be related to the configurations
2. Compiling fsbl from source code using vitis and compiling it using petalinux are different. Is petalinux also using the same source code?

Waiting for your valuable feedback.

Thanks & Regards
Vishav

[JH]

Hi,

you mean you has use our petalinux template or did you create a new project (petalinux-create --type project --template zynq --name <PROJECT_NAME>)?

I tried to create same template (one from trenz) in petalinux2020.1 but got error when I run
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petalinux-config --get-hw-description

The error says Error: Failed to create workspace directory
Therefore I created the project using zynq template and did the changes manually.

you must create from scratch, template works mostly only for the specified vivado/petalinux version. And do not forgot to change also device tree.

I tried running hello world. With the default fsbl (the one comes in prebuilt) hello world works. With the new fsbl (using vitis 2020.1 and using source code from Trenz), the error is problem in running u-boot. I also created flash_fsbl (using vitis 2020.1 and using source code from Trenz) but it doesn't help too.

also when you use older Vivado HW manager (18.3 for example)? -> you can download Vivado LabTools (programmer part only).

And you can't use complete  19.2 fsbl template in 20.1. Use Xilinx deffault 20.1 template and add our changes. --> most things are done in separate files, only some parts of Xilinx default FSBL was changes to include our C files.

br
John