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Validation failed for parameter 'PSU UIPARAM DDR CWL(PSU__DDRC__CWL)'

Started by Yourguen023, June 18, 2020, 02:41:01 PM

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Yourguen023

Hi,

I'm new in the FPGA field, so please be exhaustive in your explanations.

I'm trying to use a Trenz TEBF0808 +Trenz TE0808-04-6BE21-A. I use Vivado 2019.2 with Linux Ubuntu 18.04.4 LTS.
I downloaded TE0808-test_board_noprebuilt-vivado_2019.2-build_3_20200122142231 file.
I followed the instructions until the "Create Block Design".

I have the following errors in Vivado and have no idea how to solve it :

[IP_Flow 19-3478] Validation failed for parameter 'PSU UIPARAM DDR CWL(PSU__DDRC__CWL)' with value '16' for BD Cell 'zynq_ultra_ps_e_0'.  Supported CAS Write Latency for Speed Bin 2400  with Operating Freq 800 { 9 11 }

[IP_Flow 19-3478] Validation failed for parameter 'PSU UIPARAM DDR CL(PSU__DDRC__CL)' with value '17' for BD Cell 'zynq_ultra_ps_e_0'. Supported CAS Latency for Speed Bin 2400  with Operating Freq 800 { 12 }.This field does not need to be modified when Read DBI is enabled.

[IP_Flow 19-3478] Validation failed for parameter 'PSU UIPARAM DDR CWL(PSU__DDRC__CWL)' with value '16' for BD Cell 'zynq_ultra_ps_e_0'.  Supported CAS Write Latency for Speed Bin 2400  with Operating Freq 800 { 9 11 }

[BD 41-1273] Error running apply_rule TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
    ::xilinx.com_bd_rule_zynq_ultra_ps_e::apply_rule Line 29



If you can give me any leads.
Thank you in advance


JH

Hi,
do you have Vivado 2019.2 or Vivado 2019.2.1? In case without the patch, can you install 2019.2.1 patch (This is possible over Xilinx Information center)

QuoteI followed the instructions until the "Create Block Design".
Which of these step did you mean?
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignFlow

The the BD design will be generated normally completely when you run "_create_linux_setup.sh" and start board selection guide.
--> can you send me the whole log file until the error occuress the vivado.log file will be generated in the subfolder ../StarterKit/v_log

PS: we offer the design also with prebuilt binaries to test the board directly.

br
John



Yourguen023

Quotedo you have Vivado 2019.2 or Vivado 2019.2.1? In case without the patch, can you install 2019.2.1 patch (This is possible over Xilinx Information center)

I have Vivado 2019.2. Next the board implementation, I have to install Petalinux and the version I use is 2019.2. Won't that interfere? (Petalinus 2019.2 works with Vivado 2019.2.1 ?)

QuoteWhich of these step did you mean?
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignFlow

Yes, exactly this document, sorry.

QuoteThe the BD design will be generated normally completely when you run "_create_linux_setup.sh" and start board selection guide.

Ah... So my generation wasn't complete. I thought it was.

Quote--> can you send me the whole log file until the error occuress the vivado.log file will be generated in the subfolder ../StarterKit/v_log

Attached, the log file.

QuotePS: we offer the design also with prebuilt binaries to test the board directly.

I probably missed it, I'll try to find it and test the bord with it. 

Thank you very much for your help.

BR
Camille




Yourguen023

I finally found the binaries:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0808/Reference_Design/2019.2/StarterKit/TE0808-StarterKit-vivado_2019.2-build_8_20200325083436.zip

\Downloads\TE0808-StarterKit-vivado_2019.2-build_8_20200325083436\StarterKit\prebuilt\boot_images\

Either way, as I'm new in the FPGA field and I would like to learn (especially from errors I made), I would be very pleased to know what is my mistake for the Vivado Project Generation.

BR
Camille

JH

Hi,
I've checked your log file.
this looks like some vivado problem with your OS:
QuoteWARNING: [Common 17-1496] Vivado tclapp support version doesn't have install/uninstall hooks. Please update support using ::tclapp::update_support command.
....
xterm: Xt error: Can't open display: :0

which kind of linux did you use? On which is supported by Xilinx --> You can check requirements on xilinx installation guide for your version.


Quote
(Petalinus 2019.2 works with Vivado 2019.2.1 ?)
yes this works, important is both is 2019.2.

br
John




Yourguen023

Finally, I've used the prebuilt file to program the FPGA and to temporarily avoid the issue. I didn't install the 2019.2.1 patch. All was right until Vitis step.

I had 2 issues in Vitis :
1 ) I wasn't able to connect to any of the serial ports.

Solution :
sudo adduser #username dialout
sudo user mod -a -G dialout #username
reboot (very important!)

2 ) Error Lauchning the Program

QuoteCould not find ARM device on the board for connection 'Local'.
Check is the target is in :
1. Split JTAG - No operations are possible with ARM DAP.
2. Non JTAG bootmode - Bootrom may need time to enable DAP.

Solution :
cd /tools/Xilinx/Vivado/2019.2/data/xicom/cable-drivers/lin64/install_script/
sudo ./install-drivers

Everything works, I have the "Hello World" message.

Suprisingly, I don't have the 'PSU UIPARAM DDR CWL(PSU__DDRC__CWL)' issue any more.

Thank you JH