Hi,
FSBL configures whole PS normally.
For QSPI programming Xillinx need QSPI interface and bank voltages setup. On older vivado (17.2 and older), Xilinx has provide such a configuration for all parts, only in case you use 2 QSPI, you must use own FSBL. I think they changed it to get it more uniform, but they didn't thinking about the problems customer has, in case boot mode is not JTAG (which was not need until 17.2). With the special FSBL, we could this fix this issue easily. But the new problem where it depends on content(since 19.x), is really a bug of Vivado(I didn't find any way to fix it at the moment, because it doesn't depend on FSBL itself and only 7 Series seems to be influenced).
I hope Xilinx will get a grip on JTAG again, but unfortunately I am not so sure... :-(
br
John