TE0720-03-1CFA does not boot from QSPI Flash

[abcd]

I wrote a program (CPU code + FPGA bitstream) which is working fine when I start it via the debugger from SDK. Now I wanted to store this software in the QSPI flash on my TE0720-03-1CFA FPGA module. To do so, I first created a Zynq first stage bootloader project + according board support package and generated a boot image from this. I then used the "program flash" tool in SDK to write it into the flash. I ticked the "verify after flash option and SDK tells me in its console, that everything was working fine.
However, when I restart the FPGA board (reset or power off/on), the program doesn't start (nothing happens at all). The "mode" pin of the TE0720 is connected to 3.3 V.

What could be the reason for this? I should mention that the firmware on the CPLD located on the TE0720 is not the original one, I got a adapted version from Trenz which deactivated the pull ups on the Zynq (see also my other forum posts). However, I assumed that all the other CPLD functionality was not changed.

[JH]

Hi,
which carrier did you use? Did you set correct Boot Mode?
you can also try one one time to Boot same Boot.bin from SD (formate SD with FAT32).
What did you put into Boot.bin?

br
John

[abcd]

I didn't use a Trenz carrier board but a custom board where my TE0720 is mounted on. Boot mode is set to QSPI by tying the boot mode pin to 3.3 V. There isn't anything else to do as far as I understand the manual?

The boot.bin contains the FSBL *.elf file, the FPGA bitstream and the application *.elf (in the stated order).

What also came into my mind:
- When I try to start writing to the flash, the Xilinx SDK launches the debug view and after some seconds stops at some breakpoint in the first stage bootloader code. I will have to try again to provide the exact error message, it was something related to some macros "JTAG_MODE" and it complained that the current bootmode was set to QSPI. I googled and found this:

https://www.xilinx.com/support/answers/70548.html

Xilinx suggests to copy an additional line of code into the main file. However, this was not working for me. I solved it by simply choosing "skip all breackpoints".
- While running my code in debug mode I tried to read out the bootmode register by typing "mrd [0xF800025C]" in the XSCT console. I then compared the value I obtained to the datasheet and it was the pattern which should decode "QSPI" (LSB was set to 0x01).
Which SD card are you talking about? The eMMC memory on the TE0720? Unfortunately the SDK flashing tool is not able to write the program to the eMMC.

[JH]

Hi,
your AR70548 is our special FSBL for QSPI programming:
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-zynq_fsbl_flash.1

You need this modification for the FSBL which must be selected in the programming step. Into your boot.bin use your normal one.

You see also boot mode when you programm flash, xilinx vivado print a warning in case the boot mode is not JTAG.


For SD I mean external SD. We connect B2B MIO to SD levelsifter and SD card slot on the most of our carrier:
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Carriers

So QSPI writing fails or booting?
In case programming is successfully, but booting failed, add debug flags to your FSBL and connect uart before you restart. Debug flags show additional details on the console:
https://wiki.trenz-electronic.de/display/PD/Zynq+Troubleshooting+Guide
br
John

[abcd]

I'm currently not at my workplace and can't carry out those steps right now, I will do so tomorrow. I already set the debug flags and monitored the information last week, as far as I remember I only got "positive" results (no warnings, no errors I could remember right now). I will check again as soon as possible. Furthermore, I have a TE0703 carrier around, I didn't think of it but I can try what happens if I program the board there or use the SD card as you suggested.

[JH]

OK, let me know when you have the results.

br
John

[abcd]

I just tried again and the following happened:
- After creation of the boot image I clicked "program flash" with the settings in the attached picture. The console output was the following:

Code Select Expand

cmd /C program_flash -f \
C:\Users\username\Documents\path\to\bootimage\BOOT.bin -offset 0 \
-flash_type qspi_single -fsbl \
C:\Users\username\path\to\elf.elf -blank_check \
-verify -cable type xilinx_tcf url TCP:localhost:3122

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3122
Available targets and devices:
Target 0 : jsn-JTAG-HS2-210249ACD37A
Device 0: jsn-JTAG-HS2-210249ACD37A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.

Soon after starting, the program stops (progress information bar stops soon at the beginning) at some breakpoint in the fsbl main.c (first line of code I think, it opens some dissassembly but I don't understand exactly what's going on). There is no output on the UART interface.
- I then chose "skip all breakpoints" in SDK and tried again.
- This time it is doing something and seems to program the flash. I get an output on the UART console as well as the Consol window in SDK and the seem to be identical. See attached console output (too long for the forum post). The program terminates with "Flash operation successful". The only thing I recognized in the console listening is that it seems print something like the "starting message" several times.

(the following lines are only part of the entire console output, the text file contains everything).

Code Select Expand

cmd /C program_flash -f \
C:\Users\username\path\to\bootimage\BOOT.bin -offset 0 \
-flash_type qspi_single -fsbl \
C:\Users\username\path\to\elf.elf -blank_check \
-verify -cable type xilinx_tcf url TCP:localhost:3122

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3122
Available targets and devices:
Target 0 : jsn-JTAG-HS2-210249ACD37A
Device 0: jsn-JTAG-HS2-210249ACD37A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
===== mrd->addr=0xF8007080, data=0x30800100 =====
===== mrd->addr=0xF8000B18, data=0x80008000 =====
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B




U-Boot 2018.01-00071-g0018654-dirty (May 01 2018 - 11:18:16 -0600)



Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Silicon: v3.1

DRAM:  256 KiB

WARNING: Caches not enabled

Using default environment



In:    dcc

Out:   dcc

Err:   dcc

Zynq> sf probe 0 0 0


SF: Detected s25fl256s_64k with page size 256 Bytes, erase size 64 KiB, total 32 MiB

Zynq> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 210000



cmd /C program_flash -f \
C:\Users\username\path\to\bootimage\BOOT.bin -offset 0 \
-flash_type qspi_single -fsbl \
C:\Users\username\path\to\elf.elf -blank_check \
-verify -cable type xilinx_tcf url TCP:localhost:3122

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3122
Available targets and devices:
Target 0 : jsn-JTAG-HS2-210249ACD37A
Device 0: jsn-JTAG-HS2-210249ACD37A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.

cmd /C program_flash -f \
C:\Users\username\path\to\bootimage\BOOT.bin -offset 0 \
-flash_type qspi_single -fsbl \
C:\Users\username\path\to\elf.elf -blank_check \
-verify -cable type xilinx_tcf url TCP:localhost:3122

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3122
Available targets and devices:
Target 0 : jsn-JTAG-HS2-210249ACD37A
Device 0: jsn-JTAG-HS2-210249ACD37A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.

cmd /C program_flash -f \
C:\Users\username\path\to\bootimage\BOOT.bin -offset 0 \
-flash_type qspi_single -fsbl \
C:\Users\username\path\to\elf.elf -blank_check \
-verify -cable type xilinx_tcf url TCP:localhost:3122

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3122
Available targets and devices:
Target 0 : jsn-JTAG-HS2-210249ACD37A
Device 0: jsn-JTAG-HS2-210249ACD37A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
===== mrd->addr=0xF8007080, data=0x30800100 =====
===== mrd->addr=0xF8000B18, data=0x80008000 =====
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B




U-Boot 2018.01-00071-g0018654-dirty (May 01 2018 - 11:18:16 -0600)



Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Silicon: v3.1

DRAM:  256 KiB

WARNING: Caches not enabled

Using default environment



In:    dcc

Out:   dcc

Err:   dcc

Zynq> sf probe 0 0 0


SF: Detected s25fl256s_64k with page size 256 Bytes, erase size 64 KiB, total 32 MiB

Zynq> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 210000


SF: 2162688 bytes @ 0x0 Erased: OK

Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 7 sec.
Performing Blank Check Operation...
0%...sf read FFFC0000 0 10000


device 0 offset 0x0, size 0x10000

SF: 65536 bytes @ 0x0 Read: OK

Zynq> cmp.b FFFC0000 FFFD0000 10000


Total of 65536 byte(s) were the same

Zynq> sf read FFFC0000 10000 10000


device 0 offset 0x10000, size 0x10000

SF: 65536 bytes @ 0x10000 Read: OK

Zynq> cmp.b FFFC0000 FFFD0000 10000


Total of 65536 byte(s) were the same

Zynq> sf read FFFC0000 20000 10000



Total of 41616 byte(s) were the same

Zynq> INFO: [Xicom 50-44] Elapsed time = 39 sec.
Verify Operation successful.

Flash Operation Successful


However, when I restart the board, nothing happens.

[JH]

Hi,
can you enable debug flags on  your fsbl, so you can see extended outputs on boot up.


When you use custom carrier, how did  you connect controller signals:
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-4x5ModuleControllerIOs
What's your power sequencing?
Which power supply did you use? Some current limit?
Can you share parts of the schematics? B2B part? You can send it to support@trenz-electronic.de instead to upload here.

PS: your outputs are all from windows not from uart. It's only programming messages from xilinx. --> they load FSBL on zynq, which you has select (this one where Boot mode is set to JTAG on fsbl) and after initialisation they run Xilinx micro-uboot to program flash.  UART is on the MIO, which you has select in your project. So what did you use to translate UART and forward to PC? What does the Done LED after reboot?



br
John