Author Topic: Example acessing J1 of TE0703  (Read 670 times)

amamory

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Example acessing J1 of TE0703
« on: May 31, 2020, 02:44:46 AM »

I am using this kit https://shop.trenz-electronic.de/en/TE0720-03-1CFA-S-TE0720-03-1CFA-S-Starter-Kit?c=373
with Vivado 2019.2.

based on the base example, i tried to add a GPIO block and set it to use p1a.

In the bit stream generation phase it causes this error on the p1a ports.

[DRC NSTD-1] Unspecified I/O Standard: 22 out of 152 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: p1a_tri_io[21:0].

Is there an example design accessing J1 (External connector (VG96) placeholder) or J2 in TE0703 ?
or perhaps xdc file mapping all pins from J1 and J2 ?

thanks,
Alexandre

amamory

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Re: Example acessing J1 of TE0703
« Reply #1 on: May 31, 2020, 04:12:17 PM »


I did a few modifications such the the GPIO is configured to output and there is only bit.
My goal should be simple: just blink some LED in one of those external interfaces pf TE0703.

I added this constraint which connects my gpio output to the TE0720's C22 port and finally to the TE0703's J1A, pin 18 and 19
# my gpio - J1a- pin 18-19
set_property PACKAGE_PIN C22 [get_ports gpio_rtl]
set_property IOSTANDARD LVCMOS33 [get_ports gpio_rtl]

Is my logic correct ?

If yes, i still have this error

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gpio_rtl_tri_o[0].

please, give me some hints.

best regards,
Alexandre



JH

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Re: Example acessing J1 of TE0703
« Reply #2 on: June 02, 2020, 06:48:08 AM »
Hi,
to your problem: open Viado IO Planner after Synthese to check your constrains. You can also use Vivado to create xdc, it's sometime easier.


To your second question: We haven't any GPIO example.  We offer an excel pinout  planer available with cross reference between module
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_teba0841_pinout_tracelength.xlsx

br
John

amamory

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Re: Example acessing J1 of TE0703
« Reply #3 on: June 02, 2020, 04:03:07 PM »

thanks, your excel file confirmed my pin mapping is correct.

could you elaborate more on the part related to the constraints ? which kind of constraint should i put in this case where i only what to drive an external led ?

Alexandre

JH

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Re: Example acessing J1 of TE0703
« Reply #4 on: June 02, 2020, 04:26:21 PM »
Hi,
this depends on your selected bank voltage(Jumper on the TE0703) and how you connect LED. TE0720 supports up to 3.3V

See:
https://wiki.trenz-electronic.de/display/PD/TE0703+TRM#TE0703TRM-Jumper
https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

For LED with series resistor in the most cases LVCMOS33 is OK.

br
John

amamory

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Re: Example acessing J1 of TE0703
« Reply #5 on: June 04, 2020, 04:12:59 PM »
Hi,
to your problem: open Viado IO Planner after Synthese to check your constrains. You can also use Vivado to create xdc, it's sometime easier.


To your second question: We haven't any GPIO example.  We offer an excel pinout  planer available with cross reference between module
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_teba0841_pinout_tracelength.xlsx

br
John


Just to add that this file you indicated does not list support to Carrier TE0703, as displayed in the attached fig carrier.png.
The correct file was indeed 4x5_series_pinout_tracelength.xlsx.

However, the website says that both docs have support to TE0703. see web.png.

Unless it is a LibreOffice bug, it seems there is some correction to be done in the website or in 4x5_series_teba0841_pinout_tracelength.xlsx

By the way, I am using LibreOffice Version: 6.0.7.3, Build ID: 1:6.0.7-0ubuntu0.18.04.10

regards,
Alexandre


amamory

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Re: Example acessing J1 of TE0703
« Reply #6 on: June 04, 2020, 04:18:18 PM »
Just to close this issue, I figure out the problem.

I added the following constraint to set the pin in the carrier board.

set_property PACKAGE_PIN C22 [get_ports gpio_rtl]
set_property IOSTANDARD LVCMOS33 [get_ports gpio_rtl]

And Vivado gave this error.

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gpio_rtl_tri_o[0].

However, if you pay attention to the parts in bold, you will see that its only a matter of incorrect pin name in the constraint file. Once I corrected it as follows, it worked


set_property PACKAGE_PIN C22 [get_ports gpio_rtl_tri_o[0]]
set_property IOSTANDARD LVCMOS33 [get_ports gpio_rtl_tri_o[0]]


Thanks to Xilinx to the wonderful and insightful error message that leads to nowhere !!!!  :( >:(

regards,
Alexandre Amory

JH

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Re: Example acessing J1 of TE0703
« Reply #7 on: June 04, 2020, 08:57:13 PM »
Hi,
Quote
To your second question: We haven't any GPIO example.  We offer an excel pinout  planer available with cross reference between module
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_teba0841_pinout_tracelength.xlsx

Sorry my mistake, the other one was for TEBA0841 carrier (it used other B2B designators so we must create own excel sheet for this carrier).
 Excel sheet which included TE0703 carrier is :
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout
  • 4x5_series_pinout_tracelength.xlsx

PS: instead to write XDC by yourself use Vivado IO planner to generate loc constrains.


But thanks for the feedback and your solution to the problem

br
John