Problems with setting up design example. (TE0820-test_board)

[Kle]

I tried to run the example: TE0820-test_board-vivado_2019.2-build_10_20200408073444 on WIN.

vivado_create_project_guimode.cmd is not defining a top design, no design sources were added.
Constraints are found.

What I did (in short words):
I created a drive, so that the directory "test_board" is in the root and changed the settings for the board in design_basic_settings.cmd and started the script.

When starting "vivado_create_project_guimode.cmd" following happens:
Vivado version and directory found correctly.
INFO: [TE_INIT-1] Script Environment:
  Vivado Setting:       1
  LabTools Setting:     0
  VITIS Setting:        0
  SDSOC Setting:        0[/font]
Board found correctly:
INFO: [TE_INIT-4] Board Part definition:
  TE::ID:             26
  TE::PRODID:         TE0820-03-3BE21FA
Than vivado is started and starts to import the design, but no top is defined.
INFO: [TE_UTIL-2] Following block designs were found:
   J:/test_board/block_design/zusys_bd.tcl
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0820_2eg_1e:part0:2.0, FPGA: xczu2eg-sfvc784-1-e at 2020-02-13T09:32:16.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.

ERROR: [BD 5-104] A block design must be open to run this command. Please create/open a block design.
ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'current_bd_design' failed due to earlier errors.

Any Idea whats wrong at my setup ?
Thanks
   Kle

[JH]

Hi,
you has send only a part of the log (I think this one which is shown in tcl console of vivado)
Do following

   
• please erase whole project.
• Unzip again in a short folder
• run "_create_win_setup.cmd" and use selection guide to create the project (--> console menu), this will setup all correctly.

In case you has still problem, send me the log file, which is generate in test_board/v_log/vivado.log

br
John

[Kle]

Hi John,

I tried setting up the project new. But the result isthe same:  ERROR: [BD 5-104] A block design must be open to run this command

Please find the log file attached. 
    J: is my virtual drive.   The pathes J:\test_board\....  are fine.
    B: is not existing. (  TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx )

Kind regards
         Kle

[JH]

Hi,

you didn't use setup guide to create the project (run "_create_win_setup.cmd" and use selection guide to create the project ), but this should be no matter.

I've tried it out on my place, at it works fine.
I've used: TE0820-test_board-vivado_2019.2-build_10_20200408073444.zip
--> also virtual drive J, generate design with "vivado_create_project_guimode" and device "TE0820-03-3BE21FA"
I've put my log to the attachment.
Only different is that you didn't install Vitis and you has Vivado version 19.2, I use 2019.2.1. I've put also a screenshot of the version part to the attachment.
On may place it open BD design before it loads block design from tcl.

Can you install Vitis, please (This is need for SW development like FSBL...., so you need it in any case)? --> Note: Vitis includes Vivado, so you must deinstall Vivado 2019.2 at first.

PS: XILINXGIT_DEVICETREE is not necessary, it's optional.

br
John

[Kle]

Hello John,

I have installed vitis and update to 2019.2.1.

Updating the vivado  2019.2.1 makes the difference.  Now the design is found !  I can now explore the design example.

Many thanks for your help.
            Kle

[Kle]

Hello John
I see now the problem that I can not find TE::scripts. I typed this in the TCL console of vivado.

TE::pr_program_flash_binfile -swapp hello_te0820
invalid command name "TE::pr_program_flash_binfile"  see log file attached.

How to add the TE::scripts ?

In the HW-Manager I got following warning:
CRITICAL WARNING: [Labtools 27-3421] xczu3_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal.
Is there a configuration wrong. (I am using TE703+TE820)


Thanks
           Kle

[JH]

Hi,
function was renamed with 2019.2, sorry description was not correct.
it should be TE::pr_program_flash ....

You see all available TE functions when you type TE::help
TE function are only available when you open the vivado project with our batch files or when you reinitialise TE scripts.
We have some general documentation:
https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices
--> https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices#ProjectDelivery-Xilinxdevices-InitialiseTE-scriptsonVivado/LabTools
--> https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices#ProjectDelivery-Xilinxdevices-TE-TCL-Extentsions


Links to Xilinx documentation, which described how you programm device without our scripts:
https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools
--> https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools#XilinxDevelopmentTools-XilinxSoftwareProgrammingandDebugging

PS: TE0820 can also boot from SD instead of QSPI. Set Boot Mode to SD and put Boot.bin to SD card (fat32 format).



"In the HW-Manager I got following warning:
CRITICAL WARNING: [Labtools 27-3421] xczu3_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal."
This message is normally wrong when the Boot mode is unequal JTAG and PS is not programmed.

br
John

[Kle]

Hello John,

Could now run the design example.

Thanks for helping at the first steps .....

    Kle

[Kle]

Hello John,

I tried to redo the hello_te0820.  Debugging on hardware and download to FPGA is working.
But creating the boot image (boot.bin) is not working.
I used following bif:

//arch = zynqmp; split = false; format = BIN
the_ROM_image:
{
   [bootloader]J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\fsbl.elf
   [destination_device = pl]J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\test_board_3eg_1e_2gb.bit
   J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\u-boot.elf

}
When downloading the boot.bin (program flash) the bootloader starts but then an error appears.
-
Xilinx Zynq MP First Stage Boot Loader (TE modified)
Release 2019.2   May 12 2020  -  12:47:18
Device Name: XCZU3EG

--------------------------------------------------------------------------------
TE0820 TE_XFsbl_BoardInit_Custom

--------------------------------------------------------------------------------
PMU-FW is not running, certain applications may not be supported.
"Synchronous Abort" handler, esr 0x5e000000
elr: 00000000080019f8 lr : 00000000000f7b80
x0 : 00000000c2000001 x1 : 0000000000000000
x2 : 0000000000000000 x3 : 0000000000000000
x4 : 00000000080c0660 x5 : 0000000000000001
x6 : 00000000080b0148 x7 : 0000000000000002
x8 : 00000000080bfe20 x9 : 0000000000000080
x10: 00000000000009e8 x11: 00000000000f7c4c
x12: 0000000000000925 x13: 00000000000009ec
x14: 00000000000f7c6c x15: 00000000080bfe20
x16: 00000000fffb3716 x17: 0000000000000000
x18: 00000000000f7d20 x19: 00000000000f7ca8
x20: 00000000080a9000 x21: 000000000005de58
x22: 00000000ffd80600 x23: 00000000fffd8000
x24: 00000000fffd8088 x25: 00000000000c75e8
x26: 00000000001e4000 x27: 0000000000000100
x28: 0000000000000100 x29: 00000000000f7b50

Resetting CPU ...


When I start the "Program Flash Memory" from vitis i select:
- System
- Image file:  boot.bin   (the generated file)
- Flash Type: qspi-x8--dual-parallel
- FSBL File: J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\fsbl.elf

Any Idea whats worng ?

Many Thanks
              Kle

[JH]

Hi,
barmetal needs only fsbl, bitstream(optional) and application(optional)

In case you use Linux ( so also uboot), you need also PMU and ATF firmware. --> See Xilinx documentation.

On your BIF you has select Uboot!

br
John

[Kle]

Hello John,

What to select for application ?
I tried following, but the result is the same.

//arch = zynqmp; split = false; format = BIN
the_ROM_image:
{
   [bootloader]J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\fsbl.elf
   [destination_device = pl]J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\test_board_3eg_1e_2gb.bit
   J:\test_board\workspace\sdk\HelloK\Debug\HelloK.elf
}

Kind regards
           Kle

[Kle]

Hello John,

I got now the application program running.
I also modified the FPGA content (emu.bit), so that some pins are toggeling.
Downloading the emu.bit into the FPGA works. But after programming the flash I can see the application program running, but not the pins toggeling. When I download the emu.bit afterwards into the FPGA, it works (application+pins), but only until the next reset of course.
Did I put the emu.bit on the correct place ?  Is the destination correct for the bit file ? Do I have to place the bitfile also on the platform 'TE0820-03-3BE21FA' ? (There is also a bitfile)


//arch = zynqmp; split = false; format = BIN
the_ROM_image:
{
   [bootloader, destination_cpu = a53-0]J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\fsbl.elf
   [destination_device = pl]J:\test_board\workspace\sdk\TE0820-03-3BE21FA\resources\boot\emu.bit
   [destination_cpu = a53-0, exception_level = el-3]J:\test_board\workspace\sdk\HelloK\Release\HelloK.elf
}

Kind regards
    Kle
   

[JH]

Hi,
are you sure that you program your new Boot.bin?
--> Maybe you use older one... or your SDK Project is linked to an older version. SDK makes a lot of copies and when you reimport XSA, it can happens that not all files are updated correctly.

br
John

[Kle]

Hello John,

Thanks for your help!
I found the problem. In my rtl the a53_0 was configured wrong, but is worked for itself. In the application the a53_0 was configured correct.
The configuration for a53_0 of the rtl was overwritten by the application, so the rtl was not working any more.
Now I have exactly the same configuration for the a53_0 and it works !!

So I am very close that I can start with my real project. The only point which is open is the access to the AXI-GPIO.
The memory configuration of the AXI_GPIO is: see mem.png.
In my application I tried to access with:

    int *gpio_in;   gpio_in  = (int *)0x0080000000;
    int *gpio_out;  gpio_out = (int *)0x0080000008;
    int c,d;
    c=127;
    *(gpio_out)=c;
    d=*(gpio_in);

In the rtl the two gpios are connected by a +1 adder.   So the correct readback would be 128.  I read back 0.

Kind regards
             Kle

[Kle]

There is an unexpected delay:
   c= getchar();
   *(gpio_out)=(int)c;
   e=(char)*(gpio_out);
   d=(char)*(gpio_in);
   xil_printf("%c=%c(%c)\n\r",c,d,e);
   d=(char)*(gpio_in);
   xil_printf("%c=%c\n\r",c,d);
In the first print the value of e (readback GPIO-out) is correct and the value d is wrong. (old value)
In the second print the value of d is correct.

The chain is AXI-GPIO-OUT  =>  +1  => AXI_GPIO_IN.  The +1 is done with logic, so it should be ready within one clock.

Also inserting a delay (e.g. sleep(1)) before the first read of d turns the value of d to the correct value.
Any idea where the delay could be and how long it is ?

Thanks
      Kle

[Kle]

Problem solved now  !
The little keyword volatile solved the issue.

volatile int *gpio_in;   gpio_in  = (int *)0x0080000000;

Thanks for all contribution.
               Kle