Custom Mipi adapter over FMC connector

[SaW]

Good Morning,
We purchassed a module TE0820 and a carrier board TE0701 sometimes ago and are looking through creating an adapter board for camera MIPI using the FMC connector of the carrier Board.
for this we would have the Mipi_clk, and the 4 data _lane + the I2C and signal of trigger going though the fmc toward the mipi connector.
Here we have a small issue and your help would be of the most valuable ^^'

We observed that we have 2 banks going to the fmc, bank 64 and 66.
In the vivado design we have the possiblity (with the gui application of the mipi to connect our Clk and data lane to bank 64/66/65)
following the recommendation in the MIP_DPHY datasheet we opted for the bank66 with the pin C1/B1 (Mipi_CLK) G1/E1/F2/E4 (data lane0 to3). These configurations fixe the bank 66 with the MIPI_DPHY_DCI and so a VCCO of 1,2volts. we wanted to link the i2c on the same bank with the pin G6 and F6 aswell but we encounter a conflict because the i2C needs to be powered with a vcco of 1,8volts.
We thought of exchanging the i2c pin and the trigger ones to the other Bank 64 but after reading the schematic it seems that whatever we fix on the .xdc in vivado, both banks will end up having the same voltage later? Or we missread it? 

thank you for your help in advance
best regards

[JH]

Hi,
so fare as I know FMC standard doesn't allow mix voltages for VADJ dependes IOs.
In case you use 1.2V for VADJ, you must add I2C levelshifter to your card
so you should add I2C levelshifter to your adapter and use LVCMOS1.2V for I2C from FPGA side.
br
John

[SaW]

Hi John,
thank you a lot for your answer.
One more question, we read that if the bank is configured for the mipi signals this one will define the I/O as part of the HP I/O bank and when we configured the I2C with LVCMOS on this bank (LVCMOS12) we get this error:

Code Select Expand

Bank IO standard Support: Bank 66 has incompatible IO(s) because: The I/O standard ( LVCMOS12 ) and  drive strength ( 12 ) combination is not supported for banks of type High Performance.  Move the following ports or change their properties: iic_cam1_scl_io and iic_cam1_sda_io
from this link (https://www.xilinx.com/support/answers/70907.html) the solution is to change the drive strenght to one of the accepted value, we changed for the value 8 (highest of the accpeted value) but we were wondering how it would affect the design of our custom board? (How we understood it is that it will affect the value of our resistance, so the current on this lign would not exceed 8mA)

best regards
sarah

[JH]

I think the signal edge is flattened, which normally affects the maximum frequency.
--> Maybe use 2 Pins for output?
br
John