TE0803 DDR4 Speed Bin

[simon.beaudoin]

Hi! We are using TE0803 SOM. It has the Nanya NT5AD1024M4D3 4x4Gb DDR4. We were using it in 2400R 16-16-16 configuration from the beginning because that was the default setting when using the te0803 board file. With that configuration, we noted that our 10Gig ethernet link was throttling at 1.6Gbps (iperf3). When inspecting why the same example project for 10GigE on the zcu102 board would run at 3.9Gbps (iperf3), we noticed that the it's DDR4 configuration was set to 2133P (not R). With the TE0803, we switched from 2400R 16-16-16 to 2400P 15-15-15; the performances passed from 1.6Gpbs to 3.9Gbps right away.

My question is, what is the official speed bin of the DDR for the TE0803 embedding NT5AD1024M4D3 chips?
Is it possible to order special batches with 2400P speed instead of 2400R, seeing that it yields ~3x performance on our ethernet link?

Thanks!!

[JH]

Hi,
2400R  should be a  simple preselection for the other parameters. We use this one to get some valid timing parameter which meet Xilinx and DDR parameter specification.

DDR supports different options, see Datasheet:
https://www.nanya.com/en/Product/4170/NT5AD1024M4D3-HR

br
John

[simon.beaudoin]

Hi John, thanks for the reply.

Now, I'm having a bit of a hard time figuring out that particular datasheet... Since the chips are industrial grade, does that mean they can be operated in 2400P configuration?

I begin to realise that effectively, 2400 R/P/T/U is simply a preselection. When I look at the table at https://en.wikipedia.org/wiki/DDR4_SDRAM, I can see the difference between the configurations. Am I right to think that R/P/T/U is
only about CL-tRCD-tRP and CAS latency, like shown in the aforementioned table ?

Is simply passing the memory test exemple project from xilinx SDK a sufficient criteria to say that the ram can be operated in 2400P mode?

Many thanks

[JH]

Hi,

I begin to realise that effectively, 2400 R/P/T/U is simply a preselection. When I look at the table at https://en.wikipedia.org/wiki/DDR4_SDRAM, I can see the difference between the configurations. Am I right to think that R/P/T/U is
only about CL-tRCD-tRP and CAS latency, like shown in the aforementioned table ?

yes. You can also set to custom and select all manually. But's it's easier to select one and change if necessary.

I've check our configuration with the DDR datasheet and also run both Xilinx baremetal DDR tests. All looks OK. I will expect it will do this with your selection also.
Problem is that different setups meet specification of the DDR and Xilinx and sometimes Xilinx adapts the spec and the selection a little.

I didn't heard any problems until know and you behaviour sounds very strange.  The question why it changed the performance until you has DDR settings. I'm not sure if the speed up acceleration was caused by the DDR selection or during some other changes. --> Maybe project was corrupted or you changed also something else.  But I can't say that for sure.

Which Vivado version did you use? Did you change anything else?
Did you only regnerate FSBL witrh new XSA/HDF after DDR setup changes  or did you regenerate all? Ord did you create all from SW parts scratch?

br
John

[simon.beaudoin]

Hi, we use 2018.3. The only thing I change between my tests are the 4 configuration values of DDR in vivado. I recompile whole vivado HDF, and recompile our whole petalinux project with the different HDF.

[JH]

Hi,

I can't say for sure, but it would surprise me a bit if it's the memory settings.

You can try out to changes DDR values back to original one and regenerate all again. If it's slow down again than maybe it's because of the DDR settings. If not, than something was with your old project. In case I depends on DDR setting, I don't know at the moment how I can find out why, because our configuration also passed DDR/ZynqMP specification and memory test.

br
John