Can't get Hello World to work with TE0720 and Vitis

[tommymc]

I have been trying for days to get a simple hello world application to run on the TE0720-03-1CFA and Vitis.
I am testing with the bare module and using Platform Cable USB II for JTAG which seems to work properly.
I used the .XSA from the 2020.03.25 version of the test_board reference design in Vivado, and tried just a simple hello world application in Vitis. (V2019.2)

NOSEQ, EN1, MODE = HI
JTAGMODE = LO

The FPGA downloads fine, but the program doesn't ever seem to load into DDR
Is there any example development flow to do a simple board test with Vitis? (i.e. without Linux, etc.)

Any help would be much appreciated!
Here are the logs for errors I get:

Vitis Log:

03:10:01 INFO   : Launch script is exported to file 'C:\Users\tom\vitis\workspace_test\.sdk\launch_scripts\single_application_debug\debugger_test_app-default.tcl'
03:14:58 INFO   : Disconnected from the channel tcfchan#6.
03:14:59 INFO   : Connected to target on host '127.0.0.1' and port '3121'.
03:15:00 INFO   : Jtag cable 'Platform Cable USB II 000016e6657301' is selected.
03:15:00 INFO   : 'jtag frequency' command is executed.
03:15:00 INFO   : Context for 'APU' is selected.
03:15:00 INFO   : System reset is completed.
03:15:03 INFO   : 'after 3000' command is executed.
03:15:03 INFO   : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 000016e6657301" && level==0} -index 1' command is executed.
03:15:05 INFO   : FPGA configured successfully with bitstream "C:/Users/tom/vitis/workspace_test/test_app/_ide/bitstream/zsys_wrapper.bit"
03:15:05 INFO   : Context for 'APU' is selected.
03:15:05 INFO   : Hardware design information is loaded from 'C:/Users/tom/vitis/workspace_test/test_platform/export/test_platform/hw/zsys_wrapper.xsa'.
03:15:05 INFO   : 'configparams force-mem-access 1' command is executed.
03:15:05 INFO   : Context for 'APU' is selected.
03:15:05 INFO   : Sourcing of 'C:/Users/tom/vitis/workspace_test/test_app/_ide/psinit/ps7_init.tcl' is done.
03:15:07 INFO   : 'ps7_init' command is executed.
03:15:07 INFO   : 'ps7_post_config' command is executed.
03:15:07 INFO   : Context for processor 'ps7_cortexa9_0' is selected.
03:15:07 ERROR   : Memory write error at 0x100000. MMU section translation fault
03:15:07 INFO   : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
targets -set -nocase -filter {name =~"APU*"}
rst -system
after 3000
targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 000016e6657301" && level==0} -index 1
fpga -file C:/Users/tom/vitis/workspace_test/test_app/_ide/bitstream/zsys_wrapper.bit
targets -set -nocase -filter {name =~"APU*"}
loadhw -hw C:/Users/tom/vitis/workspace_test/test_platform/export/test_platform/hw/zsys_wrapper.xsa -mem-ranges [list {0x40000000 0xbfffffff}]
configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*"}
source C:/Users/tom/vitis/workspace_test/test_app/_ide/psinit/ps7_init.tcl
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "*A9*#0"}
dow C:/Users/tom/vitis/workspace_test/test_app/Debug/test_app.elf
----------------End of Script----------------

03:15:07 ERROR   : Memory write error at 0x100000. MMU section translation fault

---------
XSCT Log:
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121

initializing
  0%    0MB   0.0MB/s  ??:?? ETA
66%    0MB   0.8MB/s  ??:?? ETA
94%    0MB   0.6MB/s  ??:?? ETA
100%    0MB   0.5MB/s  00:01   

Downloading Program -- C:/Users/tom/vitis/workspace_test/test_app/Debug/test_app.elf
   section, .text: 0x00100000 - 0x00100a43
   section, .init: 0x00100a44 - 0x00100a4f
   section, .fini: 0x00100a50 - 0x00100a5b
   section, .rodata: 0x00100a5c - 0x00100a6f
   section, .data: 0x00100a70 - 0x00100edf
   section, .eh_frame: 0x00100ee0 - 0x00100ee3
   section, .mmu_tbl: 0x00104000 - 0x00107fff
   section, .init_array: 0x00108000 - 0x00108003
   section, .fini_array: 0x00108004 - 0x00108007
   section, .bss: 0x00108008 - 0x0010802f
   section, .heap: 0x00108030 - 0x0010a02f
   section, .stack: 0x0010a030 - 0x0010d82f

  0%    0MB   0.0MB/s  ??:?? ETA
aborting, 2 pending requests...
aborting, 1 pending requests...
Failed to download C:/Users/tom/vitis/workspace_test/test_app/Debug/test_app.elf
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x1ff984b8 (Suspended)
xsct%
[/list]

[JH]

Hi,
our reference design includes also a baremetal Hello TE0820 app (hello world in endless loop):
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-hello_te0720

I've start some documentation for basics of Vitis (but it's not finish until now):
https://wiki.trenz-electronic.de/display/PD/Vitis

br
John

[tommymc]

Thank you for the updated information.  Here are some questions/issues:

In your Vitis guide under "Create platform project for XSA" should it reference the XSA file test_board/vivado/zsys_wrapper.xsa created by the Vivado run, instead of the prebuilt board XSA file?
I tried both since I did not modify the design in Vivado but there was no difference.

Also, how do you import the hello_te0720 template to show up in the application "available templates" list?  I could not import the application into Vitis.

In any case, debugging in Vitis just does not seem to work.  The application won't load into DDR so it can be run or debugged.  It doesn't seem like the DDR is configured correctly by ps7_init?

Do you recommend I revert to using the SDK instead of Vitis to develop on the TE0720 for now?

Thanks,

-Tom

[JH]

Hi,

In your Vitis guide under "Create platform project for XSA" should it reference the XSA file test_board/vivado/zsys_wrapper.xsa created by the Vivado run, instead of the prebuilt board XSA file?

it'S no matter, but use this one from Vivado folder, in case you did not use my scripts.

Also, how do you import the hello_te0720 template to show up in the application "available templates" list?  I could not import the application into Vitis.

https://wiki.trenz-electronic.de/display/PD/Vitis#Vitis-Includelocalrepositories

In any case, debugging in Vitis just does not seem to work.  The application won't load into DDR so it can be run or debugged.  It doesn't seem like the DDR is configured correctly by ps7_init?

Did you select correct assembly variant? --> we offer TE0715 with different SoC and DDR options.
Which article name has your module(you can also send me the serialnumber instead and I can check)?

Vitis or older SDK is not matter.

Download includes also prebuilt Boot.bin which can be use to boot from SD or QSPI. Did you test it?
br
John

[tommymc]

Hello,

I was able to build hello_te0720 applications.  I had lost the repositories when I re-started the project.
I still get the memory access error when trying to download and debug with that application.

I can program the test BOOT.BIN to flash, and it seems to run OK.

My board is TE0720-03-1CFA SN 609258 and 609262.  I have tried both boards and have the same problem.
I selected variant #6 with create_win_setup.cmd for this module.

[JH]

Hi,

My board is TE0720-03-1CFA SN 609258 and 609262.  I have tried both boards and have the same problem.
I selected variant #6 with create_win_setup.cmd for this module.

that's correct.

an program the test BOOT.BIN to flash, and it seems to run OK.

Your? Our our prebuilt one? --> In case you use our prebuilt one, you can see Hello TE0720 in endless loop on UART. You can use for example putty for uart -->
Select Connection type:Serial
Speed:115200
And on Serial line: COMx      --> replace x with the number of your COM port, which was given by your WinOS. --> see device manager.

At the moment I think it's some SW problem with Vitis. WhichOS did you use? On WinOS, kill one timer hw_server.exe manually on task manager and reconnect. Does it help?
Which carrier did you use?

br
John

[tommymc]

Hi,

I am using Windows 10 and Vivado 2019.2 (I tried 2019.2.1 update and it did not help)
I fully re-installed Vivado and Vitis to make sure it was working properly.

I am working with my own carrier board and the Platform Cable USB II for JTAG.
Today I have obtained a TE0703-06 board for additional testing and here is what I have found:

Running on the TE0703 board with Vitis, trying to debug the hello_TE0720 application had the same memory access error I see trying to debug on my carrier board.
I then programmed the QSPI flash with the provided hello_TE0720 BOOT.BIN and FSBL using the TE0703 board. (I used "Program Flash" in Vitis to do this)
After this, I was able to debug and step through the application running on the TE0703 board, and serial output worked.

I then moved that module to my carrier board, and now I can debug in Vitis with the Platform Cable USB II JTAG.

So I am confused.  Is Vitis not able to initialize the FPGA properly for debug without first running the FSBL burned in the QSPI?
Even with SD boot mode set on the TE0703, the application can be debugged in Vitis once the QSPI has been programmed.

At this point I can develop on my carrier platform with a working module, but I don't seem to have found a solution for this issue.
Do you know what could be happening?

Thank you very much for your help with this.

-Tom

[JH]

Hi,

Xilinx has always had some problems with JTAG debugging. There are just too many dependencies that can disrupt JTAG. The system which is running on the Zynq (it can block JTAG access), the drivers, Vitis software itself...  Vitis is new and maybe they forgot to write some registers, which are necessary for JTAG debugging and this is done by the design now. In this case it's only a bug which will may be fixed in the next version.  Some bugs will be listed here: https://www.xilinx.com/support/answers/72773.html

I myself try to use the debugger as rarely as possible.

br
John

[tommymc]

Hello,

Yes, it seems like it is a problem with the JTAG interface in Vitis.  Maybe it is timing related.

It seems necessary to run the TE:sw_run_vitis script to create the correct XSA file for the module before running Vitis.   Is that correct?

That script doesn't work anymore when I open the test_board project.  Where is that script in the test_board reference design, and how can I make it available again?

Thanks again for your help,

-Tom

[tommymc]

Follow Up:

Hello, it turns out that this solution is not working.

What is happening is the QSPI is initializing the Zynq system, and loading the pre-programmed BOOT.BIN code, but the JTAG cable is still not downloading the application.

I am able to debug in Vitis, but even though the debug source shows my current project, I can see with the disassembly view that the code loaded is still from the QSPI boot.

So to summarize, it seems the JTAG interface on the Trenz TE0703 works properly, but the Xilinx Platform Cable USB II is not working.
I am going to try to re-install the drivers and also try to search for a solution on the Xilinx forums.

-Tom

[JH]

Hi,

It seems necessary to run the TE:sw_run_vitis script to create the correct XSA file for the module before running Vitis.   Is that correct?

yes it starts also " write_hw_platform -fixed -force  -include_bit -file ${TE::VPROJ_PATH}/${TE::PB_FILENAME}.xsa" from Xilinx

That script doesn't work anymore when I open the test_board project.  Where is that script in the test_board reference design, and how can I make it available again?

you must reinisilise scripts, use cmd file to open project again or add TCL Button with this setup:
https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices#ProjectDelivery-Xilinxdevices-InitialiseTE-scriptsonVivado/LabTools
This button can be use to reinitialise the scripts from the project.

I am going to try to re-install the drivers and also try to search for a solution on the Xilinx forums.

maybe you can share the results also here if somebody on  Xilinx forum  find out the reason.

br
John

[tommymc]

I have found the solution!

Platform: Windows 10, 2019.2 Webpack Install / TE0720 + custom carrier with FreeRTOS application development in Vitis

It seems the drivers for the Platform Cable might not get installed correctly with the Vivado+Vitis installer. (I've tried 3 times)
Here are the steps I took and now it is working reliably with TE0720 JTAG on my carrier for both Vivado and Vitis downloads and full debug:

Plug in Platform Cable and use Windows device manager to uninstall the Platform cable driver.

Unplug USB and then install driver manually by running device driver installer for DLC10:

..\Xilinx\Vivado\2019.2\data\xicom\cable_drivers\nt64\dlc10_win10\install_xpcwinusb.cmd

DLC10 is Platform Cable USB II - Not sure if this would work for Platform Cable USB I (DLC9)

I did not install any other cable drivers as they may conflict?

Thanks for all your help and support!

-Tom

[JH]

Thanks to share this information.

br
John