Unable to debug project in TE0726-zynqberrydemo1

[m.t.watson]

I've followed the instructions at https://wiki.trenz-electronic.de/display/PD/TE0726+Zynqberry+Demo1#TE0726ZynqberryDemo1-hello_te0726 to create a vivado project, export the HW, and create a vitis project. I'm then trying to debug the hello_te0726 application that this creates, but am getting the error "Error while launching program: Memory read error at 0xF8F00208".

If I generate a boot image for this application and try to program the flash using prebuilt/software/m_512MB/fsbl_flash.elf the flashing process fails, but then magically JTAG debug will work on the next attempt, before breaking again for all further attempts.

Can anyone explain what I am doing wrong?

My overall goal is simply to modify the vivado project in the demo and then create a standalone vitis project that I can debug over JTAG, but doing this using the vitis GUI fails with the same error. Are the TE provided .tcl scripts and ps7init.tcl vital to get the zynqberry to work, or should it be possible to use a standard vitis hello world project with this board?

Can someone also explain the purpose of the five different .elf files provided in prebuilt/? These are fsbl.elf, fsbl_flash.elf, hello_te0726.elf, trenz_flash_fsbl.elf, and trenz_fsbl_flash.elf. These are rather confusing!

Thanks in advance

[JH]

Hi,
did you select the correct assembly variant? Which TE0726 variant did you bough?

did you build "debug" or "release" build? --> You must select debug build.

Also your Zynq system must be initialised, either with Xilinx scripts or with FSBL.  And in case older design is running on your zynq, this can also prevent access for debugging.


For Vitis usage,
you should check Xilinx documentation, I can't help much more.
https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html
https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/index.html

Your elf questions:
fsbl is "first stage boot loader", this is need to initilise your Zynq. should be generated with the xsa export from your vivado project with valid PS Configuration (we provide Board part files with a valid configuration for the different assembly variants).
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/FSBL
fsbl_flash is modified FSBL which is need since 2017.3 to program flash, when the Boot Mode is not JTAG.
https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools#XilinxDevelopmentTools-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues
--> https://www.xilinx.com/support/answers/70148.html
--> https://www.xilinx.com/support/answers/70548.html

hello_te0726.elf is a simple barmetal (means run without OS) hello world application in endless loop.
I didn't know any "trenz_flash_fsbl.elf", "trenz_fsbl_flash.elf", but if you mean or provide FSBL version, see above and:
https://wiki.trenz-electronic.de/display/PD/TE0726+Zynqberry+Demo1#TE0726ZynqberryDemo1-Application

br
John

[m.t.watson]

The variant is correct, and am I using the debug configuration.

And in case older design is running on your zynq, this can also prevent access for debugging.

I think the problem might be related to this, but how can I stop whatever is already running?

[m.t.watson]

I found the problem. It seems that the fsbl_flash application project and the prebuilt .elf compiled from it in TE0726-zynqberrydemo1 have the line forcing the bootmode to JTAG commented out, and has the initial DDR tests commented out. Forcing bootmode back to JTAG, uncommenting the DDR code, and rebuilding fsbl_flash.elf then allows the prebuilt hello_te0726\BOOT.bin boot image to be successfully flashed. Whatever was previously in my board's flash must have been interfering with the JTAG debugger, as following flashing I can now debug as normal.

[JH]

Hi,

fsbl_flash was also not built for debugging purpose, fsbl_flash is modified FSBL which is need since 2017.3 to program flash, when the Boot Mode is not JTAG.
https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools#XilinxDevelopmentTools-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues
--> https://www.xilinx.com/support/answers/70148.html
--> https://www.xilinx.com/support/answers/70548.html

Or do I understand you correctly and it was not possible for you to write the Boot.bin in Zynq Flash with the prebuilt FSBL for flash?

br
John

[m.t.watson]

Or do I understand you correctly and it was not possible for you to write the Boot.bin in Zynq Flash with the prebuilt FSBL for flash?

Correct, if you download the archive TE0726-zynqberrydemo1-vivado_2019.2-build_5_20200214101453.zip and navigate to zynqberrydemo1\sw_lib\sw_apps\zynq_fsbl_flash\src\main.c you'll find that the line required to force JTAG mode is commented out. Given my difficulties I assume zynqberrydemo1\prebuilt\software\m_512MB\fsbl_flash.elf was also compiled with this line commented.

[JH]

Hi,
template source code is included:
https://wiki.trenz-electronic.de/display/PD/TE0726+Zynqberry+Demo1#TE0726ZynqberryDemo1-SoftwareDesign-Vitis
./sw_lib/sw_apps/

I've checked the source code, it seems it was commend this example. I will discuss this with the engineer who has create this demo.
PS: I found also trenz_flash_fsbl.elf, and trenz_fsbl_flash.elf in the download, this seems to be also fragments that were not deleted after development.

John

[JH]

Hi,
it seems there are some problems with Flash programming in 19.2.
At the moment I've only some workarounds:
https://wiki.trenz-electronic.de/display/PD/TE0726+Test+Board#TE0726TestBoard-ReleaseNotesandKnowIssues

So either use our FSBL for flash (I've updated design with correct one where Boot mode is set to JTAG in fsbl) with Vivado LabTools 2018.3 --> on this version it works like expected  and described here: https://www.xilinx.com/support/answers/70548.html

or depending on flash content use either normal FSBL (in case Flash is not empty) or fsbl_flash (in case Flash is empty) with 19.2

I will try out to find out a better solution.

br
John