Project Generation - TE_Util-0 No Block-Design Export was found

[abcd]

I tried to set up the reference project provided by Trenz for a TE0745 FPGA Board:

https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/Reference_Design/2018.2/test_board

Executing the scripts under linux centos 7 is working so far. However, when vivado starts I get the following output in the tcl console:



Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/vivado_target.xdc
/home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/_i_bitgen_common.xdc
  ------
Set processing order normal for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/vivado_target.xdc
Set processing order normal for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/_i_bitgen_common.xdc
Set use for implementation only for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/_i_bitgen_common.xdc
WARNING: [TE_UTIL-0] No Block-Design Export was found in /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design, start vivado without bd-design
INFO: [TE_UTIL-2] Following block designs were found:
    ------
WARNING: [TE_UTIL-0] No Block-Design Export was found in /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design, start vivado without bd-design
INFO: [TE_UTIL-2] Following block designs were found:
    ------
INFO: [TE_INIT-139] Run project finished without Error.
  ------
-----------------------------------------------------------------------



And of course in the opened project, no block design exists. The board files are found and should be correct. I'm using Vivado 2018.2 with a floating license running in a VM (Virtual Box), the FPGA board is a TE0745-02-93E11-A.
The output in the terminal is attached to the end of this post. Any idea what could cause this issue?
Further questions I have:
- I tried both, minimum setup of CMD-files as well as maximum setup of CMD-files. Unfortunately I was not able to find any documentation which explained the difference between minimum and maximum setup. What's
  the difference?
- The number of the Trenz board is TE0745-02-93E11-A. There are no board files for this exact number, however, from the exact FPGA type (xc7z045ffg676-3) I was able to reconstruct that the board ID has to be TE0745-02-45-3EA. Also other documentation from Trenz (e.g. pictures) are referred to as this number. I hope I'd chose the correct board and if so, why is there a difference in these numbers? It's confusing.


-- Run Design with: _create_linux_setup.sh
-- Use Design Path: /home/vm_centos7/Documents/Xilinx/Test/test_board
--------------------------------------------------------------------
------------------------TE Reference Design-------------------------
--------------------------------------------------------------------
-- (c)  Go to CMD-File Generation (Manual setup)                   
-- (d)  Go to Documentation (Web Documentation)                     
-- (x)  Exit Batch (nothing is done!)                               
-- (0)  Create minimum setup of CMD-Files and exit Batch           
-- (1)  Create maximum setup of CMD-Files and exit Batch           
----                                                               
Select (ex.:'0' for min setup):
1
---------------------------Minimal Setup----------------------------
--- 1. Open design_basic_settings.sh with text editor
--- 2. Set Xilinx Installation path, default: XILDIR=/opt/Xilinx/
--- 3. Set the Board Part you bought, example: PARTNUMBER=te0726-3m
--- For available names see: ./board_files/TExxxx_board_files.csv
--- 4. Save design_basic_settings.sh
--- 5. To create vivado project, execute: ./vivado_create_project_guimode.sh
--- Use Trenz Electronic Wiki for more information:
--- https://wiki.trenz-electronic.de/display/PD/Project+Delivery
--------------------------------------------------------------------
Press [Enter] key to continue...
[vm_centos7@vm_centos7 test_board]$ /opt/Xilinx/Vivado/2018.2/settings64.sh
[vm_centos7@vm_centos7 test_board]$ ./vivado_create_project_guimode.sh
------------------------Set design paths----------------------------
-- Run Design with: vivado_create_project_guimode.sh
-- Use Design Path: /home/vm_centos7/Documents/Xilinx/Test/test_board
---------------------Load basic design settings---------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
-- Use Xilinx Version: 2018.2 --
--Info: Configure Xilinx Vivado Settings --
--Info: Configure Xilinx SDK Settings --
--Info: Configure Xilinx LAbTools Settings --
-- Info: /opt/Xilinx/Vivado_Lab/2018.2/settings64.sh not found --
--------------------------------------------------------------------
----------------------check old project exists--------------------------
Found old vivado project: Create project will delete old project!
Are you sure to continue? (y/N):
y
----------------------Change to log folder--------------------------
/home/vm_centos7/Documents/Xilinx/Test/test_board/v_log
--------------------------------------------------------------------
-------------------------Start VIVADO scripts -----------------------

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source ../scripts/script_main.tcl -notrace
-----------------------------------------------------------------------
INFO:(TE) Load Settings Script finished
INFO:(TE) Load environment script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Utilities script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Designs script finished
INFO:(TE) Load User Command scripts finished
INFO:(TE) Load SDSoC script finished
-----------------------------------------------------------------------
-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           test_board
  TE::VPROJ_PATH:           /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado
  TE::VLABPROJ_PATH:        /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado_lab
  TE::BOARDDEF_PATH:        /home/vm_centos7/Documents/Xilinx/Test/test_board/board_files
  TE::FIRMWARE_PATH:        /home/vm_centos7/Documents/Xilinx/Test/test_board/firmware
  TE::IP_PATH:              /home/vm_centos7/Documents/Xilinx/Test/test_board/ip_lib
  TE::BD_PATH:              /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design
  TE::XDC_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints
  TE::HDL_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/hdl
  TE::SET_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/settings
  TE::WORKSPACE_HSI_PATH:   /home/vm_centos7/Documents/Xilinx/Test/test_board/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   /home/vm_centos7/Documents/Xilinx/Test/test_board/workspace/sdk
  TE::LIB_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/sw_lib
  TE::SCRIPT_PATH:          /home/vm_centos7/Documents/Xilinx/Test/test_board/scripts
  TE::DOC_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/doc
  TE::PREBUILT_BI_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/software
  TE::PREBUILT_OS_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/os
  TE::PREBUILT_EXPORT_PATH: /home/vm_centos7/Documents/Xilinx/Test/test_board/../export
  TE::LOG_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/v_log
  TE::BACKUP_PATH:          /home/vm_centos7/Documents/Xilinx/Test/test_board/backup
  TE::ZIP_PATH:             /usr/bin/zip
  TE::SDSOC_PATH:           /home/vm_centos7/Documents/Xilinx/Test/test_board/../SDSoC_PFM
  TE::TMP_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/tmp
  TE::XILINXGIT_DEVICETREE: /home/xilinx_git/device-tree-xlnx
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 2
INFO:(TE) Parameter Option: --gui
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 4
INFO:(TE) Parameter Option: --clean
INFO:(TE) Parameter Option Value: 2
INFO:(TE) Parameter Index: 6
INFO:(TE) Parameter Option: --boardpart
INFO:(TE) Parameter Option Value: LAST_ID
-----------------------------------------------------------------------
INFO: [TE_INIT-129] Run TE::INIT::run_project LAST_ID 1 1 2
INFO: [TE_INIT-0] Script Info:
  Vivado Version:                             Vivado v2018.2 (64-bit)
  TE Script Version:                          2018.2.04
  Board Part (Definition Files) CSV Version:  1.3
  Software IP CSV Version:                    2.1
  Board Design Modify CSV Version:            1.1
  ZIP ignore CSV Version:                     1.0
  ---
  Start project with:                         NA
  ------
INFO: [TE_INIT-1] Script Environment:
  Vivado Setting:     1
  LabTools Setting:   0
  SDK Setting:        1
  SDSOC Setting:      0
  ------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           test_board
  TE::VPROJ_PATH:           /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado
  TE::VLABPROJ_PATH:        /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado_lab
  TE::BOARDDEF_PATH:        /home/vm_centos7/Documents/Xilinx/Test/test_board/board_files
  TE::FIRMWARE_PATH:        /home/vm_centos7/Documents/Xilinx/Test/test_board/firmware
  TE::IP_PATH:              /home/vm_centos7/Documents/Xilinx/Test/test_board/ip_lib
  TE::BD_PATH:              /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design
  TE::XDC_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints
  TE::HDL_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/hdl
  TE::SET_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/settings
  TE::WORKSPACE_HSI_PATH:   /home/vm_centos7/Documents/Xilinx/Test/test_board/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   /home/vm_centos7/Documents/Xilinx/Test/test_board/workspace/sdk
  TE::LIB_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/sw_lib
  TE::SCRIPT_PATH:          /home/vm_centos7/Documents/Xilinx/Test/test_board/scripts
  TE::DOC_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/doc
  TE::PREBUILT_BI_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/software
  TE::PREBUILT_OS_PATH:     /home/vm_centos7/Documents/Xilinx/Test/test_board/prebuilt/os
  TE::PREBUILT_EXPORT_PATH: /home/vm_centos7/Documents/Xilinx/Test/test_board/../export
  TE::LOG_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/v_log
  TE::BACKUP_PATH:          /home/vm_centos7/Documents/Xilinx/Test/test_board/backup
  TE::ZIP_PATH:             /usr/bin/zip
  TE::SDSOC_PATH:           /home/vm_centos7/Documents/Xilinx/Test/test_board/../SDSoC_PFM
  TE::TMP_PATH:             /home/vm_centos7/Documents/Xilinx/Test/test_board/tmp
  TE::XILINXGIT_DEVICETREE: /home/xilinx_git/device-tree-xlnx
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
INFO: [TE_INIT-16] Read board part definition list (File /home/vm_centos7/Documents/Xilinx/Test/test_board/board_files/TE0745_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: /home/vm_centos7/Documents/Xilinx/Test/test_board/sw_lib/apps_list.csv).
INFO: [TE_INIT-22] Read ZIP ignore list (File: /home/vm_centos7/Documents/Xilinx/Test/test_board/sw_lib/apps_list.csv).
INFO: [TE_UTIL-70] /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado was deleted.
Found ID: 8
Board part csv name check:  8 is unique on position 0.
INFO: [TE_INIT-4] Board Part definition:
  TE::ID:             8
  TE::PRODID:         TE0745-02-45-3EA
  TE::PARTNAME:       xc7z045ffg676-3
  TE::BOARDPART:      trenz.biz:te0745_45_3e:part0:1.0
  TE::SHORTDIR:       45_3e
  TE::ZYNQFLASHTYP:   qspi_single
  TE::FPGAFLASHTYP:   mt25qu256-qspi-x4-single
  ------
Generate new project (Path: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado).
INFO: [TE_INIT-69] Set Board Definition path: /home/vm_centos7/Documents/Xilinx/Test/test_board/board_files
INFO: [TE_INIT-70] Set IP path : /home/vm_centos7/Documents/Xilinx/Test/test_board/ip_lib
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/vm_centos7/Documents/Xilinx/Test/test_board/ip_lib'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.

[JH]

Hi,
did you use this zip file: TE0745-test_board-vivado_2018.2-build_04_20190918103531.zip

WARNING: [TE_UTIL-0] No Block-Design Export was found in /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design, start vivado without bd-design

can you check this folder. Script didn't find TCL export of the BD.


And yes, you can use  TE0745-02-45-3EA for TE0745-02-93E11-A is the same FPGA and Memory.

• www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/SCH-TE0745-02-45-3EA.PDF
• http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/SCH-TE0745-02-93E11-A.PDF

for new article numbers you can also use:

• https://wiki.trenz-electronic.de/display/PD/7+Series+Zynq-7000+based+modules

I will add new article names/variants to the 2019.2 update (at first I must update TEB911, after that I will start TE0745 --> I hope I will finished this this month)

br
John

[abcd]

Hello John,

yes I used the zip file you're referring to. However, I guess I found the problem: the folder you mentioned (...test_board/block_design) was somehow not there. I don't know how I managed to lose it since I copied the whole test_board folder at once. I recopied the whole project, now Vivado manages to set up the block design.

I then tried to build (generate the bitstream) the project. Starting the synthesis works fine and is executed without errors. The troubles start once I start the implementation: The implementation fails with 3 errors:



• [IP_Flow 19-3805] Failed to generate and synthesize debug IPs. ERROR: [Common 17-161] Invalid option value '0' specified for '-jobs'.
• [Chipscope 16-330] Synthesis of Debug Cores has failed
• [Chipscope 16-338] Implementing debug Cores failed due to earlier errors

Any idea on how to solve this one? I googled the error message but I couldn't find anything helpful. Restarting the VM as well as regenerating the project didn't change anything. The error seems to occur in some functionality called "opt_design".

If necessary I can provide any log files you require, the log file for the implementation (.../vivado/test_board.runs/impl_1/runme.log) is attached to this post (I renamed it into a .txt since .log is somehow not allowed for upload here).

The output of the tcl console is this:

Code Select Expand


Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/vivado_target.xdc
/home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/_i_bitgen_common.xdc
  ------
Set processing order normal for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/vivado_target.xdc
Set processing order normal for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/_i_bitgen_common.xdc
Set use for implementation only for /home/vm_centos7/Documents/Xilinx/Test/test_board/constraints/_i_bitgen_common.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design/zsys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zsys_bd
  TE::PR_TOPLEVELNAME: zsys_wrapper
  ------
  TE::IS_ZSYS:         true
INFO: [TE_UTIL-2] Following block designs were found:
   /home/vm_centos7/Documents/Xilinx/Test/test_board/block_design/zsys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0745_35_1c:part0:1.0, FPGA: xc7z035fbg676-1 at 2018-11-23T12:31:46.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD_TCL-3] Currently there is no design <zsys> in project, so creating one...
Wrote  : </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd>
create_bd_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:30 . Memory (MB): peak = 6138.453 ; gain = 72.973 ; free physical = 2761 ; free virtual = 7384
INFO: [BD_TCL-4] Making design <zsys> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zsys".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: 
trenz.biz:user:labtools_fmeter:1.0 xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:vio:3.0 xilinx.com:ip:xlconcat:2.1  .
create_bd_cell: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 6207.801 ; gain = 54.461 ; free physical = 2678 ; free virtual = 7333
Wrote  : </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd>
Wrote  : </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/ui/bd_4addb273.ui>
Adding cell -- trenz.biz:user:labtools_fmeter:1.0 - labtools_fmeter_0
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_0
Adding cell -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_1
Adding cell -- xilinx.com:ip:vio:3.0 - vio_0
Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <zsys> from BD file </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd>
INFO: [BD 41-1662] The design 'zsys.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote  : </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd>
Wrote  : </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/ui/bd_4addb273.ui>
VHDL Output written to : /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/synth/zsys.vhd
VHDL Output written to : /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/sim/zsys.vhd
VHDL Output written to : /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/hdl/zsys_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block labtools_fmeter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
Exporting to file /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/hw_handoff/zsys.hwh
Generated Block Design Tcl file /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/hw_handoff/zsys_bd.tcl
Generated Hardware Definition File /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/synth/zsys.hwdef
generate_target: Time (s): cpu = 00:00:38 ; elapsed = 00:01:08 . Memory (MB): peak = 6348.414 ; gain = 119.941 ; free physical = 2529 ; free virtual = 7210
INFO: [TE_HW-34] Generate top level wrapper
update_compile_order: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 6348.418 ; gain = 0.004 ; free physical = 2515 ; free virtual = 7209
update_compile_order: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 6348.418 ; gain = 0.000 ; free physical = 2501 ; free virtual = 7195
INFO: [TE_INIT-139] Run project finished without Error.
  ------
-----------------------------------------------------------------------
update_compile_order -fileset sources_1
open_bd_design {/home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd}
Adding cell -- trenz.biz:user:labtools_fmeter:1.0 - labtools_fmeter_0
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_0
Adding cell -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_1
Adding cell -- xilinx.com:ip:vio:3.0 - vio_0
Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <zsys> from BD file </home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd>
launch_runs impl_1 -to_step write_bitstream
[Mon Feb  3 08:31:21 2020] Launched zsys_util_ds_buf_0_0_synth_1, zsys_processing_system7_0_0_synth_1, zsys_labtools_fmeter_0_0_synth_1, zsys_vio_0_0_synth_1, zsys_util_ds_buf_1_0_synth_1, zsys_xlconcat_0_0_synth_1, synth_1...
Run output will be captured here:
zsys_util_ds_buf_0_0_synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/zsys_util_ds_buf_0_0_synth_1/runme.log
zsys_processing_system7_0_0_synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/zsys_processing_system7_0_0_synth_1/runme.log
zsys_labtools_fmeter_0_0_synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/zsys_labtools_fmeter_0_0_synth_1/runme.log
zsys_vio_0_0_synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/zsys_vio_0_0_synth_1/runme.log
zsys_util_ds_buf_1_0_synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/zsys_util_ds_buf_1_0_synth_1/runme.log
zsys_xlconcat_0_0_synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/zsys_xlconcat_0_0_synth_1/runme.log
synth_1: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/synth_1/runme.log
[Mon Feb  3 08:31:23 2020] Launched impl_1...
Run output will be captured here: /home/vm_centos7/Documents/Xilinx/Test/test_board/vivado/test_board.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 6378.207 ; gain = 13.781 ; free physical = 2466 ; free virtual = 7160


[JH]

Hi,
is there a special reason why you use VM for Vivado?

how many CPUs did you use in your VM?

"-jobs" defindes cpus which are use to generate the design.
Did you use our scripts or GUI to run synthesis?

When you press Generate Block Design, or Run Synthesis or Run Implementation, you can select number of Jobs (CPUs). What did you select?
In case you use our scripts for build process (runs synthesis, implement and bitgen ), than it use normally 4 GPUs default, maybe this is set to zero by Vivado if four is not available.

br
John

[abcd]

Thanks for your hint what the "-jobs" means, this was helping a lot

I'm using a VM because my license server is also running in the same VM and I wasn't able to access the license server from the host OS.

I just checked and it seems that only one CPU core was available in the VM. I used the GUI command "Run Implementation" as well as the Trenz script (TE::hw_build_design -export_prebuilt). The error I obtained was the same in both cases. When I run the synthesis I have to select a number of jobs. The only option available there was "1".

So I changed the number of cores in the VM machine to 2, restarted and tried the implementation again. It is working now, I'm now able to generate the bitstream. So this means that the problem is rather coming from the VM (not enough CPU resources) than from vivado itself.

Regarding my original post: When I'm generating the scripts to create the project (_create_linux_setup.sh) I have to chose between minimum and maximum setup of CMD-scripts. What is the difference between these to options?

[JH]

Hi,

"Regarding my original post: When I'm generating the scripts to create the project (_create_linux_setup.sh) I have to chose between minimum and maximum setup of CMD-scripts. What is the difference between these to options?"

In 2018.2 reference design _create_linux_setup(bat/sh) copies only some files into the basic project folder which are used to setup and generate the project and some optional files to programm FPGA, open SDK with prebuilt hdf... for Linux are not all files available.  --> so for linux OS max and min are the same.

I've some basic description for project delivery (Wiki is always for the newest version, but the basics are the same):
https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices
2019.2 has new features, for example select device over console menu which works also on linux.

I'm using a VM because my license server is also running in the same VM and I wasn't able to access the license server from the host OS.

You use a floating licence or node-locked (normally locked to ETH MAC) license?


PS: you should spend you VM min 4 cpus and 8GB RAM.

br
John
 

[abcd]

You use a floating licence or node-locked (normally locked to ETH MAC) license?

I'm using a floating license.

PS: you should spend you VM min 4 cpus and 8GB RAM.

I'll see what I can do...RAM is not a problem but the CPU will probably be.

Thanks for your quick responses!