TEBF0808: FPGA ILA Debug through J12 (XMOD Header)

[msattine]

Hi, I am trying to connect to TEBF0808 starter kit JTAG interface for FPGA debug.


I opened a h/w server in host computer and tried connecting through hardware manager in vivado. USB from host is connected to J12 header. Vivado h/w manager is not detecting it.

Is this the right way? Or do I have to use PSJTAG header for ILA debug?

[JH]

Hi,
which clk did you connect to your ILA core? From PS? Did you initialise PS? As long as PS is not initialised, this clk not available. Bitfile do not initialise PS.
br
John

[msattine]

Hi John,
    I am running Petalinux with default build. I am with the impression that the PL initialization is taken care based on below observation(please correct me if I am wrong).

I have a small design in PL with AXI interface. I have two clocks going from PS to PL. I am able to read and write to the AXI registers with which I concluded that PL is initialized. I wrote a simple application using /dev/mem for this.

Regards,
Mohan.

[JH]

Hi,

petalinux can also control PS-PL clks. Did you use the second PS-PL CLK for ILA? Did you update your petalinux with the new HDF where the second PS-PL CLK is also enabled?

br
John

[msattine]

Hi John,
  Yes, I did update the hdf file.

The way I am doing it right now is below:
- I first open a serial console in host and reset the device and login through serial console (J12 used as UART)
- Then change the static IP settings through serial console
- Login through ssh from another prompt
- Close the serial console, now I am expecting it to be used as JTAG (Please let me know if I am wrong)
- Open h/w server in host PC and connect from h/w manager in vivado (running on another server)

Regards,
Mohan.

[JH]

Hi,

can you create a Boot.bin with simple barmetal hello world and FSBL. Did you see your ila core there?

We also disabled some kernel settings on or reference designs, which makes trouble with Xilinx debug core in the past. I don't know which module you use, so:
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-Kernel
https://wiki.trenz-electronic.de/display/PD/TE0807+StarterKit#TE0807StarterKit-Kernel
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-Kernel

--> it's the same kernel setup on all three module series.


PS: You can use JTAG and UART over serial console parallel. FTDI has to ports which are handled separately in WinOS. One is JTAG and the second one is uart.

br
John

[msattine]

Hi John,
         After some more debug, I realized that windows firewall is blocking the hw_server connection. I resolved this by disabling firewall for this application. Thanks for the help.

I am seeing another issue when using both UART and JTAG together. When I connect debugger the UART connection is lost. Same is the case when I use ethernet. Is this something that you observed earlier? What should I do to use both together?

Regards,
Mohan.

[JH]

Hi,
disable kernel setting for CPU CLK scaling. this caused this issue. See link in my last mail.
br
John

[msattine]

Hi John,
           It solved the issue. Thank you very much.

Regards,
Mohan.