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Can not program TE0720-03-1CF with TE0701-04

Started by sythe, December 20, 2019, 02:37:16 PM

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sythe

Hello,

The setup I use is behaving very flaky.

Most of the time I am not able to program/flash the TE0720. It is not consistent and I have no clue why.
It hangs in "Performing programming flash" aka "Preparing for programming flash".



****** Xilinx Program Flash
****** Program Flash v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-251633000746A
Device 0: jsn-JTAG-ONB4-251633000746A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
===== mrd->addr=0xF8007080, data=0x30800100 =====
===== mrd->addr=0xF8000B18, data=0x80008000 =====
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x000FA240 =====
READ: IO_PLL_CFG (0xF8000118) = 0x000FA240
===== mrd->addr=0xF8000108, data=0x00030008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x00030008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B




U-Boot 2018.01-00073-g63efa8c-dirty (Oct 04 2018 - 08:24:48 -0600)



Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Silicon: v3.1

DRAM:  256 KiB

WARNING: Caches not enabled

Using default environment



In:    dcc

Out:   dcc

Err:   dcc

Zynq> sf probe 0 0 0



I am using the modified Trenz fsbl and the Trenz Hello world example.
My PS is just a bare Zynq7 processing system with the uart0 and 1 enabled only.

I have tried to run the Hello World application by launching it on targer.
It then complains about the DONE pin not being high.
Resetting or powering off does not resolve the issue.

best regards,

Simon


JH

Hi,
for flash programming you must also specify FSBL on Vivado/SDK GUI. Which one did you use? --> Try out our prebuilt FSBL for flash programming.
br
John

sythe

I re-installed Vivado 2018.3 and the BSP for the TE0720 board on a different machine.

Somehow this worked. Guess I had some history, either from an upgraded Vivado or project, which was hindering.

br,

ST


JH

Hi,

good to hear that it works now. Thanks for informing me.

br
John