Author Topic: New to TE0722 in combination with TE0790, it works but some questions remain  (Read 519 times)

bstuif

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Hi I am new to the TE0722 in combination with the TE0790,

I got it working, which means the Zynq is recognized from Vivado and I am able to load my own bit-file directly into the FPGA.

However some questions remain:
1) Especially after I load the precompiled bit file, the FPGA becomes hot quickly. Its temperarture will settle just above 81 degrees celcius. Is this proper and expected behaviour?
2) Intermittently the connection is lost and the FPGA reloads its configuration, is this due to the limited power supply, because only the TE0790 is providing power?
3) Is it possible to program the S25FL127SABMFI101 QSPI FLASH directly from Vivado? If so, is there a compatible FLASH device that I can select, because Cypress is not in there.

Thanks for your help!


JH

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Hi,

Quote
1) Especially after I load the precompiled bit file, the FPGA becomes hot quickly. Its temperarture will settle just above 81 degrees celcius. Is this proper and expected behaviour?
60-70 is normal because it's very small. 
PS: you can not load only bitstream, if you do this you has a mixed design. PS configuration from a very old demo which is shipped at the moment and your PL design. --> You use PS-PL CLKs from the older design, not from your Vivado design configuration.
Start with the reference design (Download includes also Boot.bin for QSPI) flash (correct flash setup for your assembly version, see -->test_board/board_parts/board_files/TE0722_board_files.csv odf the download)
--> https://wiki.trenz-electronic.de/display/PD/TE0722+Test+Board
Pay attention when you create your own FSBL,TE0722 is without DDR, FSBL must be modfied see:
https://wiki.trenz-electronic.de/display/PD/DDR+less+ZYNQ+Design

Quote
2) Intermittently the connection is lost and the FPGA reloads its configuration, is this due to the limited power supply, because only the TE0790 is providing power?
you should not use XMOD for power supply (it's works only for very small designs):
https://wiki.trenz-electronic.de/display/PD/TE0722+Getting+Started

Quote
Is it possible to program the S25FL127SABMFI101 QSPI FLASH directly from Vivado? If so, is there a compatible FLASH device that I can select, because Cypress is not in there.
yes, correct flash setup for your assembly version, see -->test_board/board_parts/board_files/TE0722_board_files.csv odf the download
--> depending on your vivado version the name can be slightly changes.
See also Xilinx documents for programming:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264#Vivado/SDK/SDSoC-XilinxSoftwareProgrammingandDebugging

br
John

bstuif

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Hi John,

Today I finally got some time to follow your instructions.
It took me a while to figure out that I should load the design from the SDK.
Once I had figured that out it was all working nicely fairly quickly.

I have managed to load the reference design in FLASH.
However after turning on the power i need to apply a manual reset otherwise
the Si1143 sensor is not recognized properly.

This may have something to do with the power not being clean enough during startup.

Thanks for your help!

Cheers!


JH

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Hi,
Quote
However after turning on the power i need to apply a manual reset otherwise
the Si1143 sensor is not recognized properly.
Do you have problems with I2C access? Or what is the problem?
SI1143 can be reset via I2C, see:
https://www.silabs.com/documents/public/data-sheets/Si114x.pdf
so reset it via software during power up.
br
John

bstuif

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Hi John, thanks for the tip.

At the moment I have a working design (software+hardware) but I haven't been able to put it in FLASH yet.
Somehow Vivado does not want to generate the mcs file, it says QSPI4x is not suported when I try to generate the mcs file.

I guess I should look it up in Xilinx documentation.

Cheers!

JH

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Hi,
for zynq should use *.bin format.
*.BIF for Boot.bin definition is included in the reference design.
We use SDK to generate Boot.bin
--> open SDK with HDF
--> generate FSBL (use or template or modify default for DDR less --> this is important).
--> right click on the fsbl project and select generate boot files

The easiest way for application is to put your C code directly into FSBL with is default running in OCM of the Zynq.
But there are also other ways
--> generate block ram and connect to zynq --> set correct linker scripts for application
or
--> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842377/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

br
John

bstuif

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Hi John,

Using your FSBL template I have now a FSBL that I can load via JTAG and debug.
I have not been able to write the BOOT.bin file that includes this FSBL to QSPI FLASH, I have no idea why FLASH programming fails using that BOOT.bin file.

When I don't modify anything of this FSBL it seems to hang inside the
TE_FsblHookBeforeHandoff_Custom(void) function.
Specifically on the xil_printf("A03") statement.
In the terminal it seems that somewhere shortly after printing "Xilinx First Stage Boot Loader for DDR less   " the baudrate is changed?
I don't get any xil_printf debug output after that.

Anyway, I am looking for a spot to insert my own code into this FSBL.
And if possible I would like to be able to use the regular
Code: [Select]
printf functionality, instead of
Code: [Select]
xil_printf.

Alternatively, it would be nice if the FSBL would simply start the second executable inside the BOOT.bin image.

Any further experiments need to wait until after the hollidays though.

Happy hollidays for everyone!


JH

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Hi,
printf is much bigger as xil_printf --> as long as you run your code in OCM you has limited memory.

in case you want to add standalone application instead to write your code into fsbl, you can do following.
1. change linker script and use OCM separate (pay attation what you overwrite)
2. Add block RAM and use Block RAM for elf.
3. use Flash: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842377/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

br
John