TE0803 custom carrier power up sequence

[joseer]

Hello,

We need to develop a custom carrier PCB board for this SOM, and I'm trying to figure out if we've got to follow any particular sequence to power it up.

According this: https://wiki.trenz-electronic.de/display/PD/TE0803+TRM#TE0803TRM-PowerandPower-OnSequence  the SOM already follows a zynq ultrascale compatible power on sequence/criteria.
I had a look to the power on sequence on the TEBF0808 board: https://wiki.trenz-electronic.de/display/PD/TEBF0808+TRM#TEBF0808TRM-Power-OnSequenceDiagram and all is done by the CPLD, where can I see what sequence is exactly following the CPLD? could this CPLD be replaced by other IC to accomplish same task or would be recommended to carry over the CPLD (u39) design? 


Thanks.

[joseer]

I forgot to add that our carrier board would only require to have the following functionalities:
- USB3x4 hub
- SD (for OS booting)
- CAN
- Ethernet

So I'm looking to the simplest solution to power up properly the SOM and minimise number of components as much as possible....

[JH]

Hi,
CPLD is not needed, but with CPLD you can modify power sequencing later, if needed.
The easiest way is to put all Power Enable on(minimum power up sequencing is done by module). Only pay attentions for variable fpga bank power and periphery. This must be managed by the carrier. --> Power bank power and perihpery (see also Xilixn datasheet) on when module is powered up (use output voltage of the module or power good signal (different one available for different power domains --> so use the correct one)).
PS: we offer also altium projects of the TEBF0808 and TEBT0808 and the CPLD source code:
  https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBF0808/REV04/HW_Design
  https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBF0808/REV04/Firmware
  https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBT0808/REV01/HW_Design

br
John

[joseer]

Hi John,

Many thanks for your helpful answer, I'd like just to clarify/summarise some points:

CPLD is not needed, but with CPLD you can modify power sequencing later, if needed.

That gives good flexibility but in our case we're looking for a fix setup which minimise pcb size and components...

The easiest way is to put all Power Enable on(minimum power up sequencing is done by module). Only pay attentions for variable fpga bank power and periphery. This must be managed by the carrier. --> Power bank power and perihpery (see also Xilixn datasheet) on when module is powered up (use output voltage of the module or power good signal (different one available for different power domains --> so use the correct one)).

Having a look to the TEBF0808 schematic we've got the next 'main' power rails:

MOD_EN --> enable module power
1.8V and FMC_VADJ --> bank power
3.3V_PER -> peripherals power

Power up sequence to follow (please correct me if wrong):
1. The module power (MOD_EN) rail in the carrier can be fixed to enable, so when the carrier is power up, it will intermediately power up the SOM (TE0803).
2. The carrier will wait for the power good signal from the SOM and then it will enable the bank power and on board (carrier) peripherals power rails.

Would the above power sequence (carrier+SOM) work fine like that?

Regarding the TE0803 dc/dc enable and good signals (https://wiki.trenz-electronic.de/display/PD/TE0803+TRM):

Can the enable signals (EN_LPD, EN_FPD, EN_PL, EN_DDR...etc) be set enable form start?

What good signal I should check is on  before power up banks and peripherals?


Best regards.

[JH]

Hi,

That gives good flexibility but in our case we're looking for a fix setup which minimise pcb size and components...

Can the enable signals (EN_LPD, EN_FPD, EN_PL, EN_DDR...etc) be set enable form start?
--> See TEBT0808 --> we add jumper but yes all high and module will enable this parts like it should

Steps (please correct me if wrong):
1. The module power (MOD_EN) rail in the carrier can be fixed to enable, so when the carrier is power up, it will intermediately power up the SOM (TE0803).
2. The carrier will wait for the power good signal from the SOM and then it will enable the bank power and on board (carrier) peripherals power rails.

yes

What good signal I should check is on  before power up banks and peripherals?

depends on your usages and on which part of the SoC your periphery is connected.
See also:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf
--> page 15ff

For PS (and MIOs) EN_LPD, EN_FPD, EN_DDR, EN_PS_GT(if used) ... is important.
For PL it's EN_PL and GTH enables (EN_GT_R if used)
https://wiki.trenz-electronic.de/display/PD/TE0803+TRM#TE0803TRM-Power-OnSequenceDiagram
Connect also SI5338 to the I2C bus of the module, if needed--> it's not programmed, so you need PS or external programmer to write a configuration on runtime.

br
John 

[joseer]

Hi,

Thanks again for the support and  info.,

For PS (and MIOs) EN_LPD, EN_FPD, EN_DDR, EN_PS_GT(if used) ... is important.
For PL it's EN_PL and GTH enables (EN_GT_R if used)

So to summarise, assuming all SOM enable signals are set(high)/needed (EN_LPD, EN_FPD, EN_DDR, EN_PS_GT, EN_PL, EN_PL,EN_GT_R  ) from default, should I follow the next sequence?:

1. Power up module (MOD_EN rail)
2. wait for the next good signals to be asserted by the SOM:
LP_GOOD
PG_FPD
PG_PL
PG_DDR
PG_PSGT
PG_GT_R
PG_VCU_1V0
3.Power up banks and on board (carrier) peripherals (1.8V, FMC_VADJ and 3.3V_PER).

would it that work fine with the TE0803?

On the other hand, is the PG_PL signal depending of the bank power? or it will come on when only the MOD_EN power rail is applied?

[JH]

Hi,

would it that work fine with the TE0803?

it seems to be ok.

On the other hand, is the PG_PL signal depending of the bank power? or it will come on when only the MOD_EN power rail is applied?

No, see:
https://wiki.trenz-electronic.de/display/PD/TE0803+TRM#TE0803TRM-PowerandPower-OnSequence
or see schematics:
https://wiki.trenz-electronic.de/display/PD/TE0803+Resources
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0803/REV03/Documents
br
John

[joseer]

Hi John,

Thanks for the links now everything is clear and it looks quite straightforward.

I finally decided to use a CPLD to manage the power up, like that will give us more flexibility, but I'll use a smaller version (LCMXO2-256HC) as it will be only dedicated to manage the power up sequence.

I saw that the CPLDs on the TEBF0808 board get programmed in cascade using another TE0790 (https://wiki.trenz-electronic.de/display/PD/TEBF0808+TRM#TEBF0808TRM-JTAGInterface), the plan is to use only one JTAG pin connector and TE0790 for both (CPLD, SOM) and select them through jumpers, the intention is not to program the CPLD very often.

[JH]

Hi,
use JTAG enable pin of the Lattice CPLD to switch JTAG, so you can route JTAG through the CPLD. --> easy multiplex JTAG
--> we do this on other boards and carrier.

vg
John

[joseer]

Hi,

That looks better/cleaner option, thanks for the suggestion!.

Best regards.

[joseer]

Hi John,

I'm trying to get my head around this CPLD/JTAG multiplexing...

My plan is to power the whole TE0790 to 3.3v and connect all signals (JTAG + XMODs) to the CPLD bank0 (powered at 3.3v), and then multiplex them through bank1 powered to 1.8V (as it is the PS voltage).

Did you do successfully something like that with this CPLD type?

Thanks.
Best regards.

[JH]

Hi,
TEBF0808, the second XMOD.
--> depending on JTAG sell you has both CPLD in the chain or the FMC JTAG.

Or TE0820 (CPLD as JTAG levelshifter --> and JTAG Enable to select CPLD or FPGA) with TE0706 (has XMOD (TE0790) adapter and JTAG goes directly to B2B of the module). See
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/REV03/Documents
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV03/Documents

br
John

[joseer]

Hi,

Thanks for the info., so just to clarify,  in order to be able to use the TE0709-03 for both CPLD and SOM I'll have to:

- Power TE0709-03 to 3.3v.
- Multiplex the JTAG signals using the JTAGENB CPLD pin as selector. It will also act as levelshifter as well between 3.3v (JTAG xmod side) and 1.8v (SOM side).
- Levelshift (3.3v -> 1.8v) the UART/GPIO XMOD signals using the CPLD.

Would the above work?

[JH]

Hi,
TE0790 is configurable:
https://wiki.trenz-electronic.de/display/PD/TE0790+TRM#TE0790TRM-BlockDiagram
Use 3.3V Pin open and connect VIO Pin to your carrier JTAG voltage which is used for CPLD JTAG (to XMOD connector). And use Jumper on TE0790 as On,OFF, OFF ON.
In case you source TE0730 also from carrier, connect 3.3V is also possible.  Than set TE0790 to On, OFF, OFF, OFF.
br
John

[joseer]

Use 3.3V Pin open and connect VIO Pin to your carrier JTAG voltage which is used for CPLD JTAG (to XMOD connector). And use Jumper on TE0790 as On,OFF, OFF ON.

With that setup, the TE0790 will take the power from vbus,  and the JTAG signals will be 3.3V,  is that Correct? Wouldn't be a problem if they are connected to the SOM (TE0808)?

If the above is correct I can power VIO to 1.8v and connect the xmod signals straight to the SOM, right?

Thanks.

[JH]

Hi,
you told me you want to use CPLD on your system:

- Multiplex the JTAG signals using the JTAGENB CPLD pin as selector. It will also act as levelshifter as well between 3.3v (JTAG xmod side) and 1.8v (SOM side).

if you want to connect JTAG directly to SoC, you must use SOC bank voltage. in case of TE0808 it's 1.8V --> see TEBF0808.
all depends on your pcb design...

VIO is voltage from TE0790 CLPD Bank (which works is like a levelshifter). --> this should come from the carrier
3.3V is core voltage of the XMOD.  --> this can come from the carrier or the on board power regulator

br
John

[joseer]

Hi John,

Thansk for your reply,

Yes, that's right, the SoC uses 1.8v so I assumed that I will have to connect JTAG at 1.8v level.

But I'm getting confused after looking at the TEBF0808 schematic, and here: https://wiki.trenz-electronic.de/display/PD/TEBF0808+TRM#TEBF0808TRM-JTAGInterface ,the JTAG 3.3v signals (J12) look to me directly connected to the SOM https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0803/REV02/Documents/SCH-TE0803-02-04EV-1EA.PDF (SoC 1.8v bank level), without any voltage translation, what am I seeing wrong here?

[JH]

Hi,
TEBF0808 Module JTAG connected directly to the first xmod.
I wrote:

TEBF0808, the second XMOD.
--> depending on JTAG sell you has both CPLD in the chain or the FMC JTAG.

Or TE0820 (CPLD as JTAG levelshifter --> and JTAG Enable to select CPLD or FPGA) with TE0706 (has XMOD (TE0790) adapter and JTAG goes directly to B2B of the module). See
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/REV03/Documents
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV03/Documents

the second xmod is this one which shared the second JTAG with FMC JTAG.

So check TE0820 and TE0706 there it's realised like you want to do.
br
John