TE0720 - Ethernet does no work

[Stonebull]

Hello,
I have a question that is rather Xilinx FPGA specific but maybe someone here has encounterred the same problem in the past and can give me some hints.

The problem is that I am not able to get the Zynq ethernet/dma example project (bare-bone) from Xilinx to work. The initialization of the emacps, dma and interrupt controler works fine, although the program gets stucked waiting for a dma transmit interrupt that never happens.

I am using the Trenz FPGA board TE0720 with the TE0701 Carrier Board and the Vivado 2019.1 version. I started to develope in the 2018.3 version, until I upgraded to the new version and the project got converted to work with the new Vivado version - maybe this could be a reason for the problems? Other functionallities of the board however remained unaffected by the upgrade and went on working perfectly.

For boot-up I use the FSBL adapted by Trenz for the TE0720, with modifications to the LED configurations:
    LED1 (Green, 7)                             → PHY_LED0     → On - Link, Blink - Activity, Off - No Link
    LED2 (Red, 6)                                → PHY_LED1     → On - Receive, Off - No Receive,
    LED DONE (11) (CPLD: NOSEQ)      → PHY_LED2     → On - Transmit, Off - No Transmit (polarity adapted as LED is active low)

My HW configuration consists of the Trenz Reference Design (+ 2x Uart light modules). The PS has been configured to enable Enet0 & MDIO both configured to the MIO pins.


The example project sets-up the ethernet hardware in loopback mode, but I have also tested it without loopback, in combination with FreeRTOS and the FreeRTOS TCP/IP stack (with the Zynq Port) with the default test application. In this configuration the problem is the same. I never get any interrupts, neither on sending nor on receiving. Although the communication with the Marvell PHY chip over MDIO works and a link can be set-up successfully (LED1 lights up) when the FPGA is connected to a router.

Does anybody encounter a similar problem and knows what to do?

Thanks for your help.

[JH]

Hi,
we use only petalinux to test ETH. As I know, the baremetal application seldom run out of the box, but I've not much experience with this baremetal app, so I can't help much.
Xilinx has some documentation to the barmetal drivers:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841745/Baremetal+Drivers+and+Libraries
Maybe you should also search for #AR or write also to Xilinx forum how to use the xilinx example.
br
John

[Stonebull]

Hello John,
thanks for your reply. I got it to work by re-trying with simply using the trenz reference design and no additional configuration at all.
So apparently this one indeed worked out of the box and I messed something up in the past in the prior configuration of the hardware.

Best Regards,