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TEBF0808 + TE0803 petalinux boot error

Started by joseer, November 08, 2019, 12:37:25 PM

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joseer

Hello,

I've got working the TEBF0808 + TE0803 combination under xilinx 2018.3 tools. Now I need to switch to the 2018.2 version, I followed same procedure but when I tried to boot petalinux it gets stuck at the beginning only showing:


Xilinx Zynq MP First Stage Boot Loader (TE modified)
Release 2018.2   Nov  8 2019  -  10:41:09

--------------------------------------------------------------------------------
TE0803 Board Initialisation
SI5338 Init Function
Si5338 Rev 1 Initialization             Done
PCIe Reset Complete
--------------------------------------------------------------------------------


And all board lights start flashing.

(The pre-build images boot without problems)

The only difference is that I'm using the Vivado updated version 2018.2.2 instead 2018.2, would it be this the reason?

Any ideas?

Thanks.

JH

Hello,
all sources are from 2018.2 and also generated with 2018.2?
also Vivado Project, FSBL, PMU, ATF, UBoot and Linux?
br
John

joseer

Hi John,

Yes, everything has been generated with 2018.2 version of the tools, except an IP which it was generated with Vivado HLS 2018.3, I added to vivado 2018.2.2 board design and it din't give any error after generating the bitstream...

Do you think that this could hang petalinux boot?

Thanks.



JH

Hi,
can you check if PL part is programmed.  --> It stops nearly on the end so either on bitfile programming or when it starts the application (in this case Uboot and atf, if I remember correctly PMU was earlier).

Can you check if our default 2018.2 design for your assembly variant works (use Boot.bin and image.ub from prebuilt folder).

With 18.3 I've changed FSBL extantion and also changed the place to where FSBL program SI5345. --> on older version it was after GTR initialisation (this can make trouble with GTR), on newer one it's after MIO initialisation (for I2C) and before GTR initialisation.  --> that's better.  Maybe you should use one time default FSBL and add our changes from the 2018.3 design --> add all te_* files from the template and check #TE_MOD comments in the default FSBL sources. --> so you can identify what's which changes are done by xilinx and which one are come from us.

And you can also enable one time debug flags to check if you see any error code from fsbl: Link from point 5 of:
https://wiki.trenz-electronic.de/display/PD/MPSoC+Debug

br
John

joseer

Hi John,

Thanks for your reply,

I tested the pre-build images and the board boots without problems.

Also I added the te_* files and try to modify it  but unfortunately I cannot build the project, it gives compile errors...it looks like it might be tricky to mix both versions...

If the pre-build images work, why the provided zynmp_fsbl (te modified) doesn't? is there any more 2018.2 versions?

Br


JH

Hi,

you mean 2018.3 prebuilt image? Or 2018.2 prebuilt image?

br
John

joseer

Hi,

I tried 2018.2 pre-build petalinux image (image.ub, boot.BIN) and it works.

But when I build my modified vivado hw version to generate the zynqmp_fsbl.elf in SDK using 2018.2 zynqmp_fsbl (te modified) template, it doesn't boot....

Essentially I'm applying to 2018.2  same procedure as I have been successfully using for 2018.3 but without same success...

JH

Hi,
sorry I forgot, please: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate the modified FSBL
See
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0803/Reference_Design/2018.2/StarterKit
TE0803-Starterkit-vivado_2018.2-build_03-v21.pdf --> page 24 FSBL description, this was only needed on 2018.2, I don't know what caused this issue on 2018.2 but I found this solution as I start to debug this issue (--> in this case you must do nearly the same compiler changes).
br
John

joseer

#8
Hi John,

Thanks for that, now petalinux boots, but unfortunately it hangs a bit further, please find boot log attached....

The board I'm using is TE0803-02-04EV-1EA and it's got 2GB of DDR, but I saw that while booting it says 4GB instead:

I2C:   ready
DRAM:  4 GiB
EL Level:       EL2
Chip ID:        zu4ev
MMC:   sdhci@ff160000: 0 (eMMC), sdhci@ff170000: 1 (SD)
SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB

I used the provided TE0803_4EV_1E board file (2018.2 version)  in Vivado, again following same procedure as I did with 2018.3.

Not sure it this is the problem but I  modified the vivado PS settings and changed DDR to 2GB (copying same parameters as in the 2018.3 version) I'll rebuild everything and try again and see how it goes....

Do you reckon that it could be this the problem?

Any more ideas would be appreciated...

Best regards.

JH

Hi,
open petalinux\project-spec\configs\config from your petalinux project with a text editor.

comment memory settings (with #) and update hdf project again with petalinux-config --get-hw-description again. --> petalinux ignores your DDR changes after you has set it one time (this happens since one or two petalinux version). But when you remove it, it will update again with petalinux-config --get-hw-description and your new hdf.

But I'm not sure if this is the really your problem but try out please and let me know if it works.
br
John

joseer

Hi,

It didn't work it must be something else, any ideas?

Thanks.

JH

Hi,
what did you put into your Boot.bin? Can you show me your bif file please.
what's happens when you replace your uboot pmu and atf firmare with these from the 2018.2 reference design?
br
John

joseer

Hi John,

Thanks for your answer, please find attached the bif file.

Quote from: JH on November 12, 2019, 06:28:52 AM
what's happens when you replace your uboot pmu and atf firmare with these from the 2018.2 reference design?

Tried that, same result.

I'll try to simplify the hw design and see if like that boots...

JH

Hi,
try out FSBL and hello world or our provided hello TE0803 in the endless loop.

your bif looks ok, it's nearly like our one for example:
//arch = zynqmp; split = false; format = BIN
the_ROM_image:
{
  [bootloader, destination_cpu=a53-0]../../../software/3eg_sk/zynqmp_fsbl.elf
  [pmufw_image]../../../software/3eg_sk/zynqmp_pmufw.elf
  [destination_device = pl]../../../hardware/3eg_sk/Starterkit.bit
  [destination_cpu =a53-0, exception_level =el-3, trustzone]../../../os/petalinux/default/bl31.elf
  [destination_cpu =a53-0, exception_level =el-2]../../../os/petalinux/default/u-boot.elf
}

only different is the comment on the beginning, but this should no matter.
did you use SDK (bootgen) or petalinux to generate the boot.bin? You use Linux also for Vivado and SDK?


br
John

joseer

Hi,
Quote from: JH on November 13, 2019, 10:17:15 AM
try out FSBL and hello world or our provided hello TE0803 in the endless loop.
I'll try that..

Quote from: JH on November 13, 2019, 10:17:15 AM
did you use SDK (bootgen) or petalinux to generate the boot.bin? You use Linux also for Vivado and SDK?

I'm using petalinux to generate boot.bin and I'm using linux for vivado and sdk.

Thanks.

JH

Hi,
maybe check also installed packages and which kind of packages you must install for vivado/SDK and petalinux 2018.2 --> sometimes it differs between the versions.
br
John

msattine

Hi Joseer,
   Were you able to resolve this? I am facing similar issue where I get below log message in prompt
-----------------------------------------------------------
ðXilinx Zynq MP First Stage Boot Loader
Release 2019.1   Jan  2 2020  -  13:38:07
PMU Firmware 2019.1     Jan  2 2020   13:48:35
PMU_ROM Version: xpbr-v8.1.0-0
NOTICE:  ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x0
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v2.0(release):xilinx-v2018.3-720-g80d1c790
NOTICE:  BL31: Built : 13:40:58, Jan  2 2020
PMUFW:  v1.1


U-Boot 2019.01 (Jan 02 2020 - 13:17:14 +0000)

Board: Xilinx ZynqMP
DRAM:  4 GiB
usb dr_mode not found
EL Level:       EL2
Chip ID:        zu7ev
MMC:   mmc@ff160000: 0, mmc@ff170000: 1
Loading Environment from SPI Flash... SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
*** Warning - bad CRC, using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: SD_MODE1
Reset reason:   EXTERNAL
Net:   ZYNQ GEM: ff0e0000, phyaddr ffffffff, interface rgmii-id
eth0: ethernet@ff0e0000
U-BOOT for test

And it ends with a message saying 'unknown root file system'
-----------------------------------------------------------------------------------

I intended it to boot from SD card, but the message "Loading Environment from SPI Flash... SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB" says that it it trying to boot from QSPI-flash.

Hi John,
Can you please help me if I am doing something wrong? I was able to boot with prebuilt image.
I am using vivado project generated from 2018.3 with petalinux 2019.1. Is this a problem?

-
Mohan.

JH

Hi,
Quote"Loading Environment from SPI Flash... SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB"
this mean it try to load environment variables from flash --> is default enabled on uboot config, you can disable it. see Reference design documentation.

Quoteunknown root file system'
This the exact message on the console? Did you change something in uboot?

You should not mix different version of xilinx tools, this works seldom and sometimes it's also not supported by xilinx --> see for example 2019.2 dokumentation of petalinux.

So please use only 18.3 and add also changes to the default configuration like we have done it (in case you use same configuration like on our reference design) .
I will update reference design of the TE080x series to 19.2 in the next weeks.
br
John

msattine

Hi John,
          The exact message was "unrecognixed filesystem *".

I however went through further documentation in Xilinx and I found this page: https://www.xilinx.com/support/answers/69780.html.

I tried disabling eMMC (SD0) in Vivado and I got it working for now.

Thanks for the help.

-
Mohan