TE0803-02-03EG-1EA SI5338 FSBL Configuration Issue

[dongkesi]

Hi,

I refered to the StartKit 2018.2 FSBL SI5338 code to modify my configuration, and then configure my own registers. My board has no PCIE and IIC switch, so I uncomment these lines.

Code: [Select]

u32 XFsbl_BoardInit(void)
{
u32 Status;
// TE Mod : 
    xil_printf("\r\n--------------------------------------------------------------------------------\r\n");
    xil_printf("TE0803 Board Initialisation\r\n");
    Status = i2c_init();                      // Configure I2C Bus 0 driver instance
    if (Status != XFSBL_SUCCESS) {
       xil_printf("Error:I2C Init\r\n");
       goto END;
    }
/*    Status = i2c_write(0x77, 0x00,  0x10);    // Configure I2C Switch
    if (Status != XFSBL_SUCCESS) {
       xil_printf("Error: Configure I2C Switch\r\n");
       goto END;
    }
*/
    Status = si5338_init();                      // Configure clocks
    if (Status != XFSBL_SUCCESS) {
       xil_printf("Error: Configure SI5338 CLK\r\n");
       goto END;
    }
//    XFsbl_TeReset();
    xil_printf("--------------------------------------------------------------------------------\r\n");
// TE Mod finished 
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU104) || defined(XPS_BOARD_ZCU111)
/* Program I2C to configure GT lanes */
Status = XFsbl_BoardConfig();
if (Status != XFSBL_SUCCESS) {
goto END;
}

XFsbl_UsbPhyReset();
#if defined(XPS_BOARD_ZCU102)
XFsbl_PcieReset();
#endif
#else
Status = XFSBL_SUCCESS;
goto END;
#endif

END:
return Status;
}


However, the following error XFSBL_ERROR_PH_CHECKSUM_FAILED occurred during the FSBL boot. I wondered if some program segments were out of scope, so I disabled some code configurations, and the code size has been reduced, but the problem is still there.

Code: [Select]

Xilinx Zynq MP First Stage Boot Loader (TE modified)
Release 2018.2   Sep  1 2019  -  12:52:05
Reset Mode      :       System Reset
Platform: Silicon (4.0), Cluster ID 0x80000000
Running on A53-0 (64-bit) Processor, Device Name: XCZU3EG

--------------------------------------------------------------------------------
TE0803 Board Initialisation
SI5338 Init Function
Si5338 Rev 1 Initialization             Done
--------------------------------------------------------------------------------
Processor Initialization Done
================= In Stage 2 ============
SD1 Boot Mode
SD: rc= 0
File name is 1:/BOOT.BIN
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
*****Image Header Table Details********
Boot Gen Ver: 0x1020000
No of Partitions: 0x4
Partition Header Address: 0x440
Partition Present Device: 0x0
Initialization Success
======= In Stage 3, Partition No:1 =======
UnEncrypted data Length: 0xC035B
Data word offset: 0xC035B
Total Data word length: 0xC035B
Destination Load Address: 0xFFFFFFFF
Execution Address: 0x0
Data word offset: 0xF980
Partition Attributes: 0x26
Destination Device is PL, changing LoadAddress
Non authenticated Bitstream download to start now
DMA transfer done
PL Configuration done successfully
Partition 1 Load Success
======= In Stage 3, Partition No:2 =======
UnEncrypted data Length: 0x31F4
Data word offset: 0x31F4
Total Data word length: 0x31F4
Destination Load Address: 0xFFFEA000
Execution Address: 0xFFFEA000
Data word offset: 0xCFCE0
Partition Attributes: 0x117
Partition 2 Load Success
======= In Stage 3, Partition No:3 =======
Error: Checksum 0xEFF6A359 != 0
XFSBL_ERROR_PH_CHECKSUM_FAILED
Partition 3 Load Failed, 0x17
================= In Stage Err ============
Fsbl Error Status: 0x0
Any attempt to access the IIC (I use MIO IIC-0 also) will result in an error. Finally I figured out that it would be reproduce the error to execute this line in si5338_init().

Code: [Select]

Status = XIicPs_MasterSendPolled(&Iic, &test_addr, 1, IIC_ADDR);

Anybody have good ideas?

Thanks.

[JH]

Hi,
To your CHECKSUM_FAILED problem:
Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL, in case it's modified
This was needed on the 18.2 SDK otherwise I got also check sum errors(I didn't remember if it was the same message or not) --> this changes are not longer necessary on 18.3. Maybe you has the same problem.


To your SI5338 access problem:

Any attempt to access the IIC (I use MIO IIC-0 also) will result in an error. Finally I figured out that it would be reproduce the error to execute this line in si5338_init().

Did you enable the I2C controller in your PS IP? Is it the same like we use in our reference design? It seems the SI5338 did not answer. --> is the feedback from MIO which are used for I2C to SI B2B Pins designed correctly?
You can also try at first to start with out SI5338 --> deactivate SI5338 relevant GTR interfaces and check if SI5338 is accessable over I2C  in linux (i2C tools needed in rootfs) to search for I2c address --> i2cdetect...

br
John

[dongkesi]

Hi JH,

Thank you very much. My IIC works well. The "-Os -flto -ffat-lto-objects" is the root cause. I remove them from .cproject in petalinux and make my PS-GTR SGMII work.

Code: [Select]

$ grep -r "ffat-lto-objects" ./components/plnx_workspace/fsbl/fsbl
./components/plnx_workspace/fsbl/fsbl/.cproject: <option id="xilinx.gnu.compiler.misc.other.1744629094" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -Os -flto -ffat-lto-objects" valueType="string"/>
./components/plnx_workspace/fsbl/fsbl/.cproject: <option id="xilinx.gnu.compiler.misc.other.931985913" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -Os -flto -ffat-lto-objects" valueType="string"/>

But I have a new issue. After the SI5338 init done, I must hot reset the board to make SGMII ethernet work by press reset key. It looks like GTR initialization must be initialized after SI5338, Do you have any idea?

Kedong

[JH]

Hi,
see fsbl of the 18.3 starterkit reference design. I shift SI initialisation into PSU init from Xilinx --> after MIOs are initialised (needed for I2C)  and before GTR initialization will be done.

br
John

[dongkesi]

Thanks for your help. It works. I also made a temporary soft reset solution that also make PS-GTR work without too much code modification to verify board design.

Code: [Select]

static void soft_reset(void) {
        u32 RegValue;
        u32 ResetReason;
        ResetReason = XFsbl_In32(CRL_APB_RESET_REASON);
        XFsbl_Printf(DEBUG_GENERAL, "My reset reason 0x%x\r\n", ResetReason);
        if((ResetReason & (1 << 5)) == 0) {
                /* Soft reset the system */
                XFsbl_Printf(DEBUG_GENERAL,"Performing System Soft Reset\r\n");
                RegValue = XFsbl_In32(CRL_APB_RESET_CTRL);
                XFsbl_Out32(CRL_APB_RESET_CTRL,
                                RegValue|CRL_APB_RESET_CTRL_SOFT_RESET_MASK);

                /* wait here until reset happens */
                while(1) {
                ;
                }
        } else {
                XFsbl_Printf(DEBUG_GENERAL,"Performing System Soft Reset Done\r\n");
        }
}



[JH]

Hi,
your solution is also a good idea. good to hear that is works now.
br
John