Vivado: "Invalid Placement Site" while assigning pins

[IPodFan]

I want to display some numbers, just for testing purposes. For that I got myself a Digilent Pmod Seven-Segment display.
I plugged it into J1 and J2 (doesnt fit in a single Pmod, due to being two times 1 x 6) of my TE0701-06CF carrying a TE0720 SoC.
For the Pmods in found the following pins in the TrenzWiki documentation (First line stands for the  upper 6 pins of the 2x6 pmods, second line for the lower six):

J5

Y16	W16	Y18	AA18	VCC	GND
W18	W17	Y19	AA19	VCC	GND

J1

G6	C4	B6	E6	VCC	GND
A6	G7	B4	C5	VCC	GND

J2 (not found yet)

?	?	?	?	VCC	GND
?	?	?	?	VCC	GND

Now what my issue is:
Whenever I try to assign pins of J1 (and probably later also J2), Vivado tells me, that they are "Invalid Placement Sites".
Has anybody an idea how to assign the pins anyway? (Or how to use the pmods) Sadly the question in the Xilinx forum about invalid placement site, did not help me.

[JH]

Hi,
Digilent Pmod Seven-Segment display is dual PMOD:
https://store.digilentinc.com/pmod-ssd-seven-segment-display/

TE0701 J5/J6 is not compatible with dual PMOD --> different size between both connectors (not PMOD standard for dual PMOD), because VCC depends on different IO Voltages (3.3Vout and FMC_VADJ(configurable via DIP))
General notes to the PMOD connector without module
https://wiki.trenz-electronic.de/display/PD/TE0701+TRM#TE0701TRM-PmodConnectors
We offer also a new Pinout Table where you can select Carrier/module combination
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout
--> 4x5_series_pinout_tracelength.xlsx
J2 is special, there is a SD mux on the carrier, with changed firmware SD signal (MIO from PS --> dedicated Pins which will be set in PS IP) can be routed to this PMOD.

J1 and J2 are connected also to MIO (MIO from PS --> dedicated Pins which will be set in PS IP).

J5 and J6 are connected to PL, you can only use this Pin coordinates in xdc file(or Xilinx IO planner --> is easer to check if coordiante is valid).

So I think "Invalid Placement Sites" appears because you try to use MIO  Pin in PL.

PS: we offer also schematics of our carrier and modules in the download area.

br
John

[IPodFan]

So if I want to use J1 and J2 for my Pmods, I have to assign this in my PS IP, am I right?

[JH]

Hi,
than it's connected to PS interface. There are dedicated interfaces available or you can use every pin as GPIO:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

I've check only fast the overview picture of your PMOD, so it seems you can control every segment separately over this pins.

So try to use this MIOs as GPIO, in this case  you can control MIOs  via software. But if you use J2 for GPIO,  you has no SD available and you must also change firmware of the TE0701(source code is available on the download area)

You can also use J5/J6 with PL IOs (it's maybe easier), if you configure both VCC for 3.3V via DIP and Jumper --> but size between both connectors is different, so you need adapter or wire, like you must do with J1 and J2.
J5/J6 Pin coordinats: 4x5_series_pinout_tracelength.xlsx

br
John

[IPodFan]

Thank you for your research. I think I wont use J2, since I need the sd-card slot to get Petalinux working :p
I guess I´ll try something different, then using J1 and J2 since it seems not right to me.