TE0803 + TEBF0808, WRONG Polarity on FMC

[htala]

Hi, I noticed flipped polarity on some connections on FMC-FPGA connections like this:

TE0803 + TEBF0808

Conn Pin name	Desig.	Pin	Carrier Net Name	pin c	pin m	Module Net Name	FPGA Pin
FMC-LA24_P	J5	H28	B65_L17_P	J4-19	J4-19	B65_L20_N	H6
FMC-LA24_N	J5	H29	B65_L17_N	J4-17	J4-17	B65_L20_P	J6

And I want to use this signal for differential clock, How can I?

[JH]

Hi,
polarity is swapped sometimes for better signal routing. Correct polarity is this one of the symbol pin name of the SoC. You can change polarity easy in your design.

For CLK polarity is in the most cases no matter.
But you need CLK input Pin to get CLK directly into the CLK routing resources of the SoC:
https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf
Xilinx U+ Zynq Pin definition, see:
https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf
or
https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf


Route CLK over fabric into CLK routing resources of the SoC is also possible, but in this case tools has problems to calculate timings . It's not recommended and in case you still do it you must set some constrain attribute to allow vivado to do this otherwise you get an error. See Xilinx documentation.

br
John

[htala]

What about GTH clock signals for  JESDI204B which is connected to IBUFDS_GTE4 ?
Isn’t clock polarity important here?

[JH]

Hi,

why? It's a phase offset of 180°. In the most cases receiver and transceiver ref clk is not from the same crystal so you has still an offset  when you start and  and you always have a slight drift.
Receiver will make CLK recovery to align data. It is important that the accuracy of the reference CLK is within the required range.
In case data path of the lanes are swapped, you can easy invert (some protocols does it automatically). In case of JED IP core, enable debug pins and invert manually if necessary.


br
John