Author Topic: Can't program te0710's fpga  (Read 93 times)

lucas.rotava@avl.com

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Can't program te0710's fpga
« on: August 14, 2019, 10:28:15 AM »
Hi all,

first i want to let you know that i'm new to xilinx environment.

Now the problem itself. I am working with a 0710 Artix 7 module, connected to the 0706 carrier board.

I used the design reference to create a FPGA project and add some extra logic to deal with some external board of mine (through some of the GPIO available). At first i was programming the FPGA through the SDK, right before downloading the software for the microblaze. Here i noticed something strange, once the FPGA was already programmed, the SDK failed to reconfigure to the FPGA. I had to power cycle the board (then yellow LED is on) to be able to program it again.
After a while i wanted to have the FPGA configuration in flash, so i programmed the QSPI flash in the module. I managed to put the bitstream there, and now every time i turn on the board, the FPGA is configured and is working (yellow LED is off).

The problem is that now i can't program the fpga anymore, even in Vivado. And also i can't update the flash. I'm stuck with the first design i programmed in the flash.

My impression is that the CPLD in the module might be holding some of the programming signals when the FPGA is programmed and running, but i can't really verify this.

Any thoughts on this?

best regards

Oleksandr Kiyenko

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Re: Can't program te0710's fpga
« Reply #1 on: August 14, 2019, 10:42:25 AM »
Hi Lucas,

In this board CPLD just bypass JTAG signals to the FPGA and control reset. Please try to program the board with clear reference project.

Best regards
Oleksandr Kiyenko

lucas.rotava@avl.com

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Re: Can't program te0710's fpga
« Reply #2 on: August 14, 2019, 10:47:16 AM »
i tried to do it with the .bit file in the prebuilt folder of the project. But it fails to do so:

Quote
set_property PROBES.FILE {C:/Users/u23z48/Downloads/te0710-test_board-vivado_2017.4-build_07_20180329130739/test_board/prebuilt/hardware/35_2cf/test_board.ltx} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {C:/Users/u23z48/Downloads/te0710-test_board-vivado_2017.4-build_07_20180329130739/test_board/prebuilt/hardware/35_2cf/test_board.ltx} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {C:/Users/u23z48/Downloads/te0710-test_board-vivado_2017.4-build_07_20180329130739/test_board/prebuilt/hardware/35_2cf/test_board.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-2302] Device xc7a35t (JTAG device index = 0) is programmed with a design that has 1 ILA core(s).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'msys_i/vio_0' at location 'uuid_6CB1A8099D185D019F53D3091D703E51' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7a35t_0 and the probes file(s) C:/Users/u23z48/Downloads/te0710-test_board-vivado_2017.4-build_07_20180329130739/test_board/prebuilt/hardware/35_2cf/test_board.ltx.
The device design has 1 ILA core(s) and 0 VIO core(s). 0 ILA core(s) and 0 VIO core(s) are matched in the probes file(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

[edit] the reset button in the 0706 is apparently also not working. I press it but nothing changes in the module board.
« Last Edit: August 14, 2019, 10:53:13 AM by lucas.rotava@avl.com »

lucas.rotava@avl.com

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Re: Can't program te0710's fpga
« Reply #3 on: August 14, 2019, 12:54:35 PM »
I tried with another board, with an empty flash this time.

Went to Vivado hardware manager, programmed the board with the reference design. Then tried to program with my design and it does not work. I can only program the fpga after powering it off (then it is reset).
In this case, the progress bar stays in 1% for some seconds, then it vanishes, it doesn't accuse error, it says the FPGA is programmed, but the LEDs don't change (my design turns the ETH leds on, and the reference turns them off, this is how i'm seeing it).

And again, the reset button doesn't do anything.

Oleksandr Kiyenko

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Re: Can't program te0710's fpga
« Reply #4 on: August 14, 2019, 04:51:27 PM »
Hi Lucas,

in your log I don't see an actual error message, it tells that your current design and bit file you select to program is not matched (as you select bit file from prebuilt folder), but no actual "ERROR: ???" message.
As for button, it should work (reset the board), but there are 2 other factors which can affect to reset
1 - Power supply. If something wrong with the power, CPLD can generate reset by PGOOD.
2 - EN1 signal (S1D on TE0706)
Please check EN1 and PGOOD on your board.

Best regards
Oleksandr Kiyenko

lucas.rotava@avl.com

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Re: Can't program te0710's fpga
« Reply #5 on: August 19, 2019, 10:16:18 AM »
PGOOD is low.

Now i realized that the red sysled2 in the 0710 is always blinking, and apparently it shouldn't be when the fpga is programmed. The green sysled1 is on when the fpga is empty, and goes off when it is programmed.
Also EN1 has no effect…

Now, what could be the cause of the PGOOD not going high? I set all the jumpers on 0706 to position 2-3 (3.3 V). And the dip-sw in the 0706 is set as s2-ON, s3-OFF, s4-ON.

My power source says its output is 5V - 2A.

[edit] I've checked the 3.3 V and 1.5 V in the 0710 and they are apparently ok. VCCIOA, B and C are 3.3 V.

What else should i check here?

My
« Last Edit: August 19, 2019, 10:42:17 AM by lucas.rotava@avl.com »

JH

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Re: Can't program te0710's fpga
« Reply #6 on: August 19, 2019, 10:43:53 AM »
Hi,
https://wiki.trenz-electronic.de/display/PD/TE0710+CPLD#TE0710CPLD-LED
LED is blinking if Reset, EN1 or Power good from 1.8V Sense pin on U23 is low.

TE0706 has RST over push button to gnd, but no external pullup. TE0710 has also no external pullup for this pin. I've checked CPLD Firmware source code, it seems that the Pullup is missing on this cpld firmware for the reset pin.

Can you write me a email to support@trenz-electronic.de
I will send you a CPLD Firmware file with internal pullup enabled, which you can try out.
 
br
John

lucas.rotava@avl.com

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Re: Can't program te0710's fpga
« Reply #7 on: August 19, 2019, 10:59:21 AM »
sent the email!

Checked the 1.8V here and it is also ok.

JH

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Re: Can't program te0710's fpga
« Reply #8 on: August 19, 2019, 11:53:27 AM »
I've send you new CLD firmware, please let me know if it helps.
br
John

lucas.rotava@avl.com

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Re: Can't program te0710's fpga
« Reply #9 on: August 19, 2019, 12:13:51 PM »
Yes, it worked now!

One detail, the EN1 dip (S1-4) had to be configured to OFF. I got confused with the sentence in the datasheet
Quote
Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM.

So, summary, before updating the CPLD neither Reset nor EN1 switch changed anything, and the reset button was floating. After updating the CPLD. with EN1 switch set to OFF, the reset button works as expected, resetting the FPGA. And if the flash is programmed, the FPGA starts its configuration again.

Thanks guys for the help!

best regards

JH

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Re: Can't program te0710's fpga
« Reply #10 on: August 19, 2019, 12:47:09 PM »
Hi,
parts of the TRM are copy from other one and unfortunately not all was checked...
depending on modules series, not all features of the controller signals are implemented/used. So on some series EN1 does not influence power up (like TE0710). Here it does the same like the Reset Pin, it hold only prog_b low.

We have some general notes for our 4x5 modules
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-4x5ModuleControllerIOs
TE0710 CPLD Firmware description:
https://wiki.trenz-electronic.de/display/PD/TE0710+CPLD

But good to hear that is works now. I will update public CPLD firmware in the during  2 week.

br
John