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TE0720: Distributing Signals and Clocks on different PL I/O Banks

Started by Ulrich Hilsinger, August 01, 2019, 04:56:36 PM

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Ulrich Hilsinger

I'm currently working on the Hardware Design side for a TE0720-03 application.
My application requires 2 ADC outputs (each ADC providing 16 bit data + overflow flag plus symmetric ADC clock output) plus separate reference clock (LVPECL) to be used.
All clock signals should go to clock inputs, while probably only the separate reference clock will be used in the final design.

For signal integrity reasons on the board (preventing excessive line cross-overs), it would be helpful to use both, bank 33 and bank 13.
Are there any issues to be expected if either
- Clock and Data are not within one bank (e.g. clock on bank 33, data on bank 13)
- Data out of one ADC is not within one bank (e.g. bit 0 to 9 on bank 33, and 10 to 15 on bank 13, with clocks on bank 13 or 33)?
The application is not a high speed application, clock rates will be in the 10 to 100 MHz range (36 MHz for the beginning).

Thanks,
Ulrich

Oleksandr Kiyenko

Hi Ulrich,

put all data/clock lines in one bank is only critical when you going to use serdes or/and local clock buffers. For your application, you can use global clock lines and data capture in any suitable FPGA bank.

Best Regards
Oleksandr Kiyenko