I want to create an SDSoC hardware platform for a TE0803-03-4DE11-A on a TEFB0808 carrier board, I'm using SDSoC 2019.1.
I am using the project TE0803-SK0803_zusys_SDSoC-vivado_2018.2-build_03_20181112081021 as a base.
I updated all references to vivado 2018.2 to 2019.1 and the zynq_ultra_ps_e:3.2 to 3.3 in the scripts.
i also changed the 'set PARTNUMBER' to 24, for the board I'm using.
With these changes, I ran create_win_setup.cmd and it creates the project in vivado without errors.
I can export the hardware to SDK and run write_dsa successfully.
On SDK, I create an fsbl application based on the exported hardware with this warning:
"There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined" I wonder if it's safe to ignore it.
I generate the bif and bin files from the compiled elf.
Then I create an empty application called dummy_app and modify the heap and stack sizes as per Xilinx UG1236
Same warning about DDR_1
I copy all these four files (bin, bif, elf and linker script) into a new folder. I modify the bif file as per UG1236 as well.
Now in SDx, I start a new platform project, import the DSA file, create the system configuration and processor domain, but generate fails without more details. Nothing in the 'Problems' tab either.
Does anyone see anything that can be wrong?