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Maximum Density for DDR3 with x16 datawidth

Started by mhagh, June 29, 2019, 10:17:17 AM

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mhagh

Hi,

while checking out TE zynq modules, I noticed that all of those with single DDR3 chip (like TE0728) have a maximum density of 512MB (4Gb).
While Micron has larger memories with x16 data bus, I wonder why these larger ddr3 chips are not used on Zynq boards?

regards

JH

Hi,
did you check availability and prices for this ddr you ask for?

In case it's footprint compatible and all needed IOs to used higher density are connected, we can assembly on custom request(min. order is needed). If you are interested, please write  email to support@trenz-electronic.de

br
John

mhagh

Hi,
Thank you for the reply,

I just want to make sure that it is technically possible, because I've not seen any single chip ddr3 chip being used in xilinx fpga boards any-where.
As an instance this part is a 1GB DDR3 which seems to be compatible with 512MB parts which are commonly used in fpga boards:
IM4G16D3FDBG-15E

regards.

JH

Hi,
you want to create your own FPGA board? Zynq or pure FPGA device only?


You mean "IM4G16D3FDBG-15E" is the 1GByte variant? Are your sure the name is correct?
I also didn't find a  1GB single die variant which we has used, so I can't tell you out of the box if it's possible or not.

So create a Vivado design and configure DDR, like you want  to use and like you has connect and see if you can generate the project.
For zynq see also:
Fore pure FPGA see also:
br
John

mhagh

Hi,

Quoteyou want to create your own FPGA board? Zynq or pure FPGA device only?
Yes. It's a Zynq board.

QuoteYou mean "IM4G16D3FDBG-15E" is the 1GByte variant? Are your sure the name is correct?
sorry, I meant this part: IM8G16D3FCB

QuoteSo create a Vivado design and configure DDR, like you want  to use and like you has connect and see if you can generate the project.
I will try it. But at the early steps, I noticed that there is no ddr3 part larger than 512MB in pre-defined Memory parts in vivado, which may be due to a certain limitation on xilinx ddr controller.

JH

Hi,
you must check how the DDR is organized internally and if you can connect all the needed IOs on the Zynq PS DDR interface  to address whole size.
In case it's not possible with 16bit ddr, you can 2x 16 bit ddr to increase size.
br
John