Hi Ales,
thanks for your quick reply!
Currently I am indeed writing without a pause at system clock speed (125MHz) to the fifo, I will throttle this today and recheck the measurements.
I have previously tried every possible setting of the write block size, with no change at all. The jumps were identical, regardless of the setting.
Concerning the DMA_Reset() behaviour:
I think this is a systematic problem. If you look at the NPI_WRITE_ENGINE process in dma_write_path.vhd and suppose the rst_global signal is high, the wr_xfer_done_i signal will be set to 1. After a XPS_NPI_DMA_Reset() call from the software, the xfer_write signal will also be 0. So we can assume the xfer_write is 0 and npi_wr_state is IDLE. As soon as the reset signal goes to 0, the if condition asking for xfer_write = '1' will return false, jumping into the else part. There we can see that wr_xfer_done_i is set to 0.
This means, if I am correct, that after a reset the XPS_NPI_DMA_Reset() the XPS_NPI_WrDone() will always return 0. There is no influence on the non blocking XPS_NPI_DMA_WriteRAM, because it does not check whether the write operation was done. The blocking variant checks and will always return 0, because it looks as if a write operation is currently in progress.
I hope you can follow my train of thoughts and please correct me, if I'm wrong

Regards,
Martijn