EthernetLite on TE0712 with TE0706

[Matthias Meier]

Hi,

I am working with TE0712 board and TE0706 carrier and Vivado 2018.2.
I tried to implement a basic Ethernet System usting AXI EthernetLite.
But when I try to test it with "Peripherals Tests" , the EmacLite examples fail.

I think that i might have a problem with the hardware, as I didn`t change anything in the software.
I have concerns especially about the Phy-Reset, but it's just a gues:
When choosing the "PHY reset out" Bitstream Generation fails. That`s why i placed my own "phy_rst_n" output in the block design, and asigned the signal to the corresponding pin (see image below).  Is there a reason why this is done using the y-adapter in test-board project? And has anybody and idea where my problem is?

Thanks alot

[JH]

Hi,
which ETH PHY did you use? This one on the TE0712 or this one on the TE0706 or both together?

For TE0712 PHY , we have it working on the reference design. For PCB REV02 we used MCS to configure the external module PLL(SI5338) and get a phase synchron CLK for ETH Lite and a second PLL output. For PCB REV01 we used a MMCM to create the phase offset, see: https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board#TE0712TestBoard-BlockDesign
-->Phase offset from MIG is to big.

Y-adapter create only access to the MII interface without connecting all interface signals manually. IP source code is include in the /ip_lib folder and does: phy_rst_n <= s_mii_rst_n;

For the second ETH PHY on the TE0706 we have at the moment only an older Vivado 16.2 example for TE0720 available.
br
John

[Matthias Meier]

Thanks for the fast reply!
I am using the PHY on the TE0712.
I totally forgot about the clock...So right now I am using the 50MHz clock provided by the SI5338 and for the entire system.

When i am trying the PeripheralsTest now, The SDK gives following errormessage:
"10:04:27 ERROR   : Cannot stop MicroBlaze. Stalled on instruction fetch"
So using this clock must have generated another issue?

[JH]

Hi,
https://wiki.trenz-electronic.de/display/PD/TE0712+TRM#TE0712TRM-Clocking
second 50MHz CLK is default not programmed.
So use MCS and our MCS firmware to reprogram on power up or use MIG output CLK on MMCM with phase offset (see PCB REV01 reference design)
https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board#TE0712TestBoard-BlockDesign

br
John