Author Topic: TE0720 Reset Signals  (Read 51 times)

nss-jacob

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TE0720 Reset Signals
« on: May 15, 2019, 03:34:36 PM »
We are currently designing our own carrier card for use with the TE0720 module and have a question about the ability to drive the PS reset to the Zynq. PS_SRST_B is driven through the CPLD on the module, but there is some advantage to having it connected out to JTAG headers for debug(Xilinx and Digilent programmers both use it as a halt signal). Is there any way to gain access to it through the CPLD, or is it driven by the CPLD in response to different JTAG operations?

Any information you can give me would be helpful.
Thank you

JH

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Re: TE0720 Reset Signals
« Reply #1 on: May 16, 2019, 11:06:11 PM »
Hi,
PS_SRST_B is not needed for JTAG. On CPLD it's constant high. CPLD does only Power ON Reset(PS_POR_B) --> See module controller IOs

Here are some additional notes, if you design your own carrier, :
We provide also Altium files of our 4x5 carrier on the corresponding download are, this helps to start up easier your own carrier.

brJohn