TE0808 XCZU15EG-1FFVC900E + TEBF0808-04A pmod access

[jarios86]

Hi!!

I have an UltraSOM+ MPSoC Module with Zynq UltraScale+ XCZU15EG-1FFVC900E and UltraITX+ Baseboard for Trenz Electronic TE080X UltraSOM+ (TEBF0808-04A) and I need to access from the PL to the pmods placed on the TEBF0808-04A baseboard. To do that, I would need to know the relation connection between the pmod pins and where are mapped to the FPGA pins. I have read some documents in order to clarify this problem but I cannot manage it with the information that I have read. The documents that I have followed are:

- TE0808 Schematics - https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0808/REV02/Documents/SCH-TE0808-02.PDF
- TE0808 TRM - https://wiki.trenz-electronic.de/display/PD/TE0808+TRM
- TEBF0808-04A Schematics - https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBF0808/REV04/Documents/SCH-TEBF0808-04A.PDF
- TEBF0808-04A TRM - https://wiki.trenz-electronic.de/display/PD/TEBF0808+TRM
- www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Pinout/TE_MASTER_PINOUT.xlsm

How can identify what pin from a pmod connector is mapped to what pin to the FPGA?? If I can do this, I can assign the FPGA pin my GPIOS in vivado I/O planing tool.

Thanks in advance,
Antonio

[JH]

Hi, which PMOD did you mean?
P2? In this case
https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBF0808/REV04/Documents/SCH-TEBF0808-04A.PDF
page 30,
signal EX_IO1...4 --> goes to CPLD page 8 where it is not used on the CPLD Firmware(https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD) --> CPLD Firmware source code is available on the download area
signal EX_IO5..7 goes uver levelshifter U33 (same page to B2B) --> B65_0...3(data) page 6 J4 and B66_T0..3(to set Direction) page 3 J1
--> From https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0808/REV02/Documents/SCH-TE0808-02.PDF
J1 page 2, J4 page 5 --> FPGA Bank 65 page 9 and Bank 66 Page 10


br
John