Author Topic: TE0720: FCLK_CLK1-3 not running  (Read 291 times)

narinx

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TE0720: FCLK_CLK1-3 not running
« on: April 17, 2019, 09:29:36 AM »
Hi all,

Up untill now I only used FCLK0 from the processing system and everything was running fine.
I then needed another fixed clock so I thought I would use FCLK1. So I connected this to some FIFOs in my design but noticed empty and full flag being high all the time. I then connected it to an output pin an saw that it is not running although when I do "report_clocks" in vivado, it reports it as a clock. So I connected all 4 clocks (and of course enabled them in the processing system) but only FCLK0 is running... I can see all 4 clocks in the xdc file and in the clock-report.
Did this happen to anyone before? Do I have to do something in software as well to start them?

Also, when I change the frequency for FCLK0 to for example 100MHz in the processing system, it remains at 50MHz after bitstream generation.. Although when doing so I can see that the xdc file is adapted accordingly. However, the clock report now states that there are no clocks present in the design...
Anyone any idea what might be going on here?

Thanks in advance!

Br,
Hans

JH

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Re: TE0720: FCLK_CLK1-3 not running
« Reply #1 on: April 17, 2019, 09:44:07 AM »
Hi,
did you regenerate FSBL, linux(in case you used it) with your new HDF?

br
John

narinx

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Re: TE0720: FCLK_CLK1-3 not running
« Reply #2 on: April 17, 2019, 09:50:43 AM »
Thanks for your reply! :-)

No I didn't.  Why is this necessary? Up until now, any change I did on the design (add PLL, change pinout, etc,..) was executed properly by just doing 'cat
fpga_design.bit >> /dev/xdevcfg'.
Is this different for when making changes to the processing system? Sorry I'm still quite new to this :-)
I'm still running the petalinux of the reference design btw.

This wouldn't explain the fact that when changing the clockfrequency, no clocks at all are reported when generating the bitstream.

Br,
Hans

JH

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Re: TE0720: FCLK_CLK1-3 not running
« Reply #3 on: April 17, 2019, 10:06:56 AM »
Hi,

in case you change something which effects PS (PS IP itself, AXI Bus Register Mapping on PL...), you must regenerate FSBL, Uboot...Linux. PS initialisation will be done with FSBL, and also Linux can for example enable/disable the outout CLKs...

So if you start with the reference design, follow the instructions of the wiki documentation (we provide some scripts to automate some steps, but there are also links to do it manually (or check Xilinx  documentation)).

br
John

narinx

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Re: TE0720: FCLK_CLK1-3 not running
« Reply #4 on: April 17, 2019, 10:15:31 AM »
Hi John,

Thanks!! I did not know this..
Will try to do so and post again when it works :-)

Br,
Hans

narinx

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Re: TE0720: FCLK_CLK1-3 not running
« Reply #5 on: April 17, 2019, 12:39:19 PM »
Worked indeed!
Thanks again!