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could not find module... xdc file will not be read for any cell of this module

Started by narinx, April 09, 2019, 02:09:26 AM

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narinx

Hi everyone,

I just bought a couple of TE0703 starter kits with a TE0720 on it.
We use these starter kits to test our prototype ASICs on bench in the lab.
We used to use the spartan sp601 board for this but since it is out of production we needed to look for an alternative, hence the TE0703..

I use Vivado 2017.4 together with the petalinux to build a project including the modified  code we used to run on the spartan.
I can generate a bitsstream and the whole thing work. cpp-code to access a custom registermap using axi,.. Controlling the PCB, Accessing the ASIC, the whole lot...
However,when, after generating the bitstream, I do a "report_clocks" no clocks are detected, the report is empty.. My design:



Critical errors:


When I run the reference design I don't get these.
I tried resetting the output products but to no effects.

What I think is weird is the fact that it mentions zsys_processing_system 7_0_0 but in the design it is called zsys_processing_system 7_0 (no second 0 at the end). I don't change any names of the blocks either....
Any Idea why this could be happening?


Thanks for your advice in advance!
Br,
Hans

JH

Hi,
I think the double zero on the name is not the problem.
There is e second attribute, when you open the properties window of the block design with the double zero (see picture on the attachment)
You can also compare on the bd file: TE0720\test_board\vivado\test_board.srcs\sources_1\bd\zsys\zsys.bd with a text editor --> is the same on the reference design.
Maybe your vivado project is corrupted.
Did you try to generate your design again on a new project?

brJohn

narinx

Hi John,

Thanks for you reply. I think I found the problem.
Will reply when I'm sure :-)

Br,

Hans

narinx

Hi,

Found the problem. I created my IPpackage after the zsys design was allready imported, causing it's component to also be in the ip. But since this wasn't there, it gave the warnings.
Modified the tcl scripts a bit and now it's gone and I get a clock report as well.
However now my design without any critical errors/timing errors doesn't work anymore ;D

Up to the next problem ;)

Thanks for the help!
Br,
Hans