Hello all,
I am working with the board TE0808 with the SOM Zynq-UltraScale U9EG-1EE. I want to ensure that the PLL_RST is set to '1' and also that the SFP1_TX_DIS is set to 0.
As I have seen in the schematic both signals goes to the CPLD chip. My question is how can I set this values and how can I read them. Is there any design flow for this kind of thing?
Thanks and best regards,
baldrism