Mask poll failed at ADDRESS: 0xFD4023E4 MASK: 0x00000010

[baldrism]

Hello all,

I am working with a custom board that uses the UltraSOM+ MPSoC XCZU9EG-1FFVC900E from Trenz.
I created a new project using the board files provided by Trenz and the bitstream was successfully created. I launched the SDK and I programmed the FPGA without problems.
The problem was when "Launching on hardware", that a message appeared with the following error:

"Error while launching program:

Timeout Reached. Mask poll failed at ADDRESS: 0xFD4023E4 MASK: 0x00000010"

I found in this forum a similar threat that suggests to comment the mask poll in the psu_init.c file, but this didn't work in my case because it fails another mask poll ADDRESS.

Do you know what is happening? Has anybody encountered a similar error? I think the problem is related with the SerDes initialization, but I don't know how to deal with it.

I would appreciate some help.

Thank you in advance and best regards,

baldrism

[JH]

Hi,
disable Xilinx init scripts or remove GTR interfaces from PS or start with our FSBL (Boot.bin without linux!) from SD and change to JTAG without power off.
Backround: Some GTR reference CLKs(genererated by the SI5345) will be initialised with our FSBL. Xilinx default init script desn't do this and so PLL Lock status failed.
br
John

[shasig]

Hi,
disable Xilinx init scripts or remove GTR interfaces from PS or start with our FSBL (Boot.bin without linux!) from SD and change to JTAG without power off.
Backround: Some GTR reference CLKs(genererated by the SI5345) will be initialised with our FSBL. Xilinx default init script desn't do this and so PLL Lock status failed.
br
John

Hello, could you describe in more detail how to do all this, preferably with examples of screenshots from vivado.  I am a new vivado user in this, and I encountered this error.

[JH]

Hi,
we didn't provide details screenshots for all steps, sorry.
--> you must check debugger configuration window

We have only some general notes and links to Xilinx documentation:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264

Is there any reason why you want to start ZynqMP with debugger? If ZynqMP is a new for you, this is not the easiest part to start. ZynqMP includes a lot of mechanism which can prevent debugger to get access

I would recommend to start with prebuilt Boot.bin and image.ub on SD, if this works, create our reference design with out changes and later if this still works on your place, start to modify.

In case you want still use debugger, maybe it's easier to do following:
Put Boot.bin with Hello TE0808 app (from reference Design) on SD and boot. --> Hello TE0808 should appears as endless loop. Switch Boot Mode to JTAG (DIP on TEBF0808 and connect JTAGagain with your SDK, as long as you did not power off the module, SI is initialised and you can run Debugger without disable this init scrips.

br
John

[baldrism]

Hi,
disable Xilinx init scripts or remove GTR interfaces from PS or start with our FSBL (Boot.bin without linux!) from SD and change to JTAG without power off.
Backround: Some GTR reference CLKs(genererated by the SI5345) will be initialised with our FSBL. Xilinx default init script desn't do this and so PLL Lock status failed.
br
John

I tried to disable the xilinx init scripts, but I had this error: "Error while launching program: Memory write error at 0x0. Instruction transfer timeout."
I search in the downloads from trenz some project done with the SOM I am usin, the 9eg_1ee but there is no examples neither the FSBL. Could you please tell me how can I obtain the FSBL?

Thanks and best regards,

baldrism

[JH]

Hi,
sorry my mistake, last time i've done this was with FSBL, and in this case it works.

So for simple SDK debugging do either:
Put Boot.bin with Hello TE0808 app (from reference Design) on SD and boot. --> Hello TE0808 should appears as endless loop. Switch Boot Mode to JTAG (DIP on TEBF0808 and connect JTAGagain with your SDK, as long as you did not power off the module, SI is initialised and you can run Debugger without disable this init scrips.
Or:
Disable GTR relates Interfaces on PS IP --> Vivado MPSoC IP --> IO/Configuration --> disable USB3 (USB0 --> USB3), PCie, SATA, DP
Regenerate Design an export HDF to SDK



For your FSBL Question:  Follow instruction:
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignFlow
Modified FSBL is included as templete. You can use our scripts to regenerate FSBL and Boot.bin or use our scripts to export HDF to SDK, in this case our FSBL is included as local repository in the SDK an you can see it as templete when you create a new app, see also https://wiki.trenz-electronic.de/display/PD/SDK+Projects

br
John

[baldrism]

Thank you very much JH,

when I disabled the DisplayPort, the SATA and the USB0 it worked. My next step is try to configure this PLL. Is there any example or configuration from Trenz that program this clock?

Thanks and best regards,

baldrism

[JH]

Hi,
it's included into the reference design FSBL: https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-zynqmp_fsbl.1
--> this FSBL works only with GTRS activated (one of them DP, SATA,USB or PCIe), I will try to make it more flexible in one of the next updates.

FSBL program SI temporary. But SI5345 has an NVM which can be programmed 2 times(not more!) in case you want to program it permanently. Some basic nots:
https://wiki.trenz-electronic.de/display/PD/Si5345

br
John

[baldrism]

Thank you very much JH,

I will take a look on that links. Please, let me ask you one more question. In my design I wanted to add a DMA, but everytime I try to enable the DDR controller the system hangs on psu_init.tcl.
I read that it is because the initialization of the processor system is not completing. Do you know if there is any example that uses the DDR controller?

Thanks and best regards,

baldrism

[JH]

Hi,
DDR is enabled with our reference design (also correct DDR settings, for the different variants). And DDR is used for example for your hello world app(if you did not change linker script) or if you use linux than from linux.
In any case if you want to get access to DDR, this must be configured by psu_init script or by the FSBL. --> This will be done before bitstream is loaded (in case you do it not manuelly from Vivado)

For DMA access to DDR we havn't examples.
br
John

[baldrism]

Hello JH,

in the preset.xml file there is a list of DDR settings. Please, see the following attached image "preset_xml.png".
However, when I try to add these settings in my Zynq, there are some errors.
In particular it says the following:
"Validation failed for parameter 'PSU UIPARAM DDR CL(PSU_DDRC_CL) with value '17' for BD Cell 'zynq_ultra_ps_e_0'. Supported CAS Latency for Speed Bin 2400 with Operating Freq 1066.56 {16}.

Therefore my system didn't work due to these DDR failures.
Do you know how can I solve that and why there are these warnings?

Thanks,

baldrism

[JH]

Hi,
follow instruction of the reference design:

• https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignFlow

18.3 design includes a console menue to select the correct assembly variant.
This should set the correct PS settings. If not, send me the generated log file (subfolder ./vlog)
br
John

[baldrism]

Thank you very much JH,

your help has been very useful.

Best regards,

baldrism