Hi,
Can anyone advise on this?:
I am looking at SCH-TE0808-04-09EG-2IE.pdf schematic.
- ref des D2 (BAT54AWT1G) is a dual diodes with cathode connected to EN_PL and LP_GOOD, anode connected to U4A Enable pin.
----[ R=10Kohm ]----PL_DCIN
En_PL --|<l-- l
|----- Enable (U4A)
LP_Good --|<l--
In this case whether the En_PL and LP_Good are set '1' or '0', U4 will not be depended on them as U4 power is only depends on PL_DCIN.
Should D2 be AND gate so that user are able to control the PL power?