Author Topic: PL power sequence  (Read 1866 times)

Leica

  • Active Member
  • *
  • Posts: 2
PL power sequence
« on: March 21, 2019, 06:53:49 AM »
Hi,

Can anyone advise on this?:

I am looking at SCH-TE0808-04-09EG-2IE.pdf schematic.
- ref des D2 (BAT54AWT1G) is a dual diodes with cathode connected to EN_PL and LP_GOOD, anode connected to U4A Enable pin.

                            ----[ R=10Kohm ]----PL_DCIN
 En_PL     --|<l--    l
                        |----- Enable (U4A)
 LP_Good --|<l--
 
In this case whether the En_PL and LP_Good are set '1' or '0', U4 will not be depended on them as U4 power is only depends on PL_DCIN.

Should D2 be AND gate so that user are able to control the PL power?

JH

  • Global Moderator
  • Hero Member
  • *****
  • Posts: 1997
Re: PL power sequence
« Reply #1 on: March 22, 2019, 08:26:13 AM »
Hi,
basic power on sequencing is done by module itself, but user can disable different power domains, so yes you can control it, see also:
br
John


Leica

  • Active Member
  • *
  • Posts: 2
Re: PL power sequence
« Reply #2 on: March 22, 2019, 09:03:42 AM »
Hi John,

I think if EN_PL (3.3V) and LP_Good (3.3V) are connected to cathode of a diode (D2), they are unable to control the enable pin of U4.
BAT54AW - reverse voltage is min 30V.

PL_Vccint will boot up on its own whether there is power from PL_DCIN.


JH

  • Global Moderator
  • Hero Member
  • *****
  • Posts: 1997
Re: PL power sequence
« Reply #3 on: March 22, 2019, 09:50:24 AM »
Hi,
it's like a logical and to get the possibility to disable this power rail.
if EN or PG signal is GND, than Enable of U4 is force to zero.

If you didn't use this pin add pullup on the EN and PG Pin, then this power rail will enabled only with PL_DCIN.

br
John