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TE0706 and TE0720 with two Ethernet PHYs

Started by DG, February 18, 2019, 02:30:46 PM

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DG


Hi there,


I would like to use TE0706 and TE0720 with two Ethernet PHYs.
For our setup, I took the hardware example 2017.4 and ported it to 2018.3. Then I removed R19 on the TE0706 and set the pinning in TE0720-SC.xdc to the appropriate pins (jumper and switch settings: chosen according to our hardware). To check, if everything is working fine, I started the peripheral test example application of the Xilinx SDK.

Unfortunately, ethernet port 1 is not passing the interrupt test. The following information is received as debug information:
---Entering main---


Running ScuGicSelfTestExample() for ps7_scugic_0...
ScuGicSelfTestExample PASSED
ScuGic Interrupt Setup PASSED

Running XDmaPs_Example_W_Intr() for ps7_dma_s...
Test round 0
XDmaPs_Example_W_Intr PASSED

Running Interrupt Test  for ps7_ethernet_0...
EmacPsDmaIntrExample PASSED

Running Interrupt Test  for ps7_ethernet_1...


The program freezes at this point.
The question is: should this example work with the described setup and software example?
Or did I overlook anything?

Kind regards,
Dino



JH

Hi,
2017.4 reference design is only for vivado 2017.4. If the projects works with other Vivado versions, depends on the version changes from Xilinx.
We have also an 2018.2 reference design online:
and 18.3 update is planned soon.

Testdesign contains prebuilt Boot.bin and image.ub for linux. Does this work?

br
John

JH


mfarnan

We are also designing a dual port Ethernet board.

Our current baseboard schematic is based on the TE0706.

Ideally there would be a Vivado reference design which we could 'adopt' as our starting point. (Did i miss this on some part of the Wiki ? ).   

We also noticed that there is a base board 6x6 (TEB0728) which has two Ethernet ports and a recent  (2013.3) reference design.

We are at the point in our schematic capture phase that we could change and use the TEB0728 design as a starting point.

So
Has anyone confirmed two Ethernet ports working on the TE0706 ?
Is there a reference design we could download which shows the two Ethernet ports working ?  (if so how does the second MAC address get set?)
Would it be sensible to switch to the TEB0728 design ? 

Any help/suggestions appreciated

Thanks,
M

DG

Hi John,


as far as I see, this reference design uses only the first ethernet port.
We cannot test ETH1 hereby, which was my concern.

Kind regards,
Dino

JH

Hi,
for second ETH we have at the moment only this old 2016.2 design online:
This works only with 16.2 second ETH works hardly ever out of the box and what's changes needed depends on Xilinx Vivado/Petalinux  version.
br
John

DG

Hi John,


if I use only the hardware part of this example project, looking like the schematic in the docs folder,
should the Xilinx Peripheral-Tests work with it?


Kind regards,
Dino

JH

Hi,
it was tested with the linux, which is included. ETH0 should works with udhcpc and the second one must be configured manually (IP), ping test should work.
We didn't use Xilinx periphery bare metal application.

I will do this design on my task list for 18.3  design updates with Wiki documentation, but I can't tell you time line for this task.
br
John

Antti Lukats

Dear DG,

we do not test with Xilinx peripheral tests. We also do not recommend to use them, they have sometimes issues. It may possible to make them work, but it is not to be expected that they always work out of the box.

For second ETH test with Xilinx peripheral tests my bet is that it will NOT work out of the box. It may be possible to make it work, but I can not estimate the time needed to figure out what is needed. Sometimes issue is as simple as setting fixed PHY address. Sometimes could be something else.

So sec

DG

Okay, thank you very much for your input!
DG