Author Topic: Setting OPTO Isolate (Port B)  (Read 575 times)

tcmichals

  • Active Member
  • *
  • Posts: 12
Setting OPTO Isolate (Port B)
« on: March 09, 2019, 05:56:34 PM »
Would like to use OPTO Isolate for Port B for the FTDI on the CYC1000 board,  OPTO Isolate Fast Serial is defined in the FTDI manual at https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf section 3.1.4.6.  The goal is to get data at greater then 3Mbps, via USB,  the FTDI chip supports 50Mbps, the current goal is just 10Mbps.

Questions:
- Would changing Port B From RS232 UART to  OPTO Isolate using FTDI FT Prog cause any issues with JTAG port? 
- Is it possible to restore the EEPROM for the FTDI to the original contents?  Is there a EEPROM image available from trenz or Arrow?

The reason for asking before changing from RS232 to OPTO Isolate, some other vendors JTAG devices using FTDI chip FT Prog app can "brick" the FTDI chip i.e. the user can restore the original operation, JTAG on Port A and Serial on Port B.

The fast serial should should still work with the standard serial drivers.




tcmichals

  • Active Member
  • *
  • Posts: 12
Re: Setting OPTO Isolate (Port B)
« Reply #1 on: March 20, 2019, 02:40:27 PM »
I have validated that changing port B Opt Isolate does not impact JTAG and virtual serial port still works with Fast Serial Mode.  Now pushing forward on verilog code to support fast serial.

Antti Lukats

  • Hero Member
  • *****
  • Posts: 501
    • Trioflex
Re: Setting OPTO Isolate (Port B)
« Reply #2 on: August 03, 2019, 05:57:34 PM »
hope you got it working, we have used it also in some projects, there is small quartus IP available (will be made available).

tcmichals

  • Active Member
  • *
  • Posts: 12
Re: Setting OPTO Isolate (Port B)
« Reply #3 on: August 04, 2019, 06:01:29 AM »
>hope you got it working, we have used it also in some projects, there is small quartus IP available (will be made available).
OK,I would like to review it.

Use the fast serial mode to connect to an Avalon master via bytes_to_packets and packets_to_bytes IP.   Attached is an example using python to control the LEDS on the board.

Here is the PDF:

1. Load the CYC1000 to FPGA
2. in the project is python directory.  It is coded to use Linux and the serial interface '/dev/ttyUSB0' if the interface different edit the code.
example: python3 avalon_loopback_serial.py
The app walks a '1' across the LEDs

It would be helpful to have a faster SDRAM interface example, for example, add SDRAM to the master using 133Mhz or 100Mhz, using Platform designer.  The end goal is use a Risc-V core instead of NIOS II,  the free version of Quartus does not support cache, floating point etc for NIOS II. 
« Last Edit: August 04, 2019, 06:10:57 AM by tcmichals »

tcmichals

  • Active Member
  • *
  • Posts: 12
Re: Setting OPTO Isolate (Port B)
« Reply #4 on: August 04, 2019, 06:06:04 AM »
Attached is the project.