Image sizes

[MFRAN]

Hi,

I am quite new to the CYC1000 and Cyclone 10LP and am wondering how large programs the flash can hold.
As I understand the boot process, the flash holds both the fpga image and the software for NIOS II.
Can anyone provide a rough estimate of the possible size of a NIOS sw that can be stored?

[plentymuseum]

On the TEI0003-01 board, I measured the amount of current that was drawn. I supplied power to the board using the VIN pin, which outputs 5 volts.
Without an FPGA design: around 60 milliampere-seconds; with our reference design: approximately 100 milliampere-seconds.

snake game

[tekskosong]

Depending on your CYC1000 board revision, the onboard SPI flash is either 8 MB or 2 MB:

[]

FPGA bitstream (10CL025): ~0.8 to 1 MB (or ~300–500 KB if compressed).
[]Available for Nios II SW: Roughly ~7 MB (on 8 MB flash) or ~1 to 1.2 MB (on 2 MB flash).
[/list]

At boot, the program typically uncompresses into the onboard 8 MB SDRAM to execute, so ~7 MB is more than enough for most Nios II applications.

[tekskosong]

The CYC1000 typically features a 64 Mbit (8 MB) SPI NOR flash (or 16 Mbit / 2 MB on older board revisions). The memory budget breaks down as follows:

[]

FPGA Configuration Bitstream (10CL025): Requires ~0.95 MB uncompressed. Enabling bitstream compression in Quartus reduces this footprint to roughly 350–500 KB.
[]Net Flash Available for Nios II Code:

[]

8 MB Board Revision: ~7.0 to 7.5 MB
[]2 MB Board Revision: ~1.0 to 1.5 MB
[/list]
[/list]

Execution Architecture: The SPI flash serves strictly as non-volatile storage. Upon boot, the bootloader copies the Nios II software image into the onboard 8 MB SDRAM (or internal M9K BRAM blocks) for runtime execution. This provides ample headroom for typical bare-metal C/C++ firmware or lightweight RTOS (e.g., FreeRTOS) deployments.

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teks kosong