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Byte write to external SDRAM

Started by Novakov, January 18, 2019, 04:55:54 PM

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I'm trying to use the SDRAM chip on SMF2000 board. I'm using provided reference design which is configured to use SMC. 32-bit and 16-bit access works correctly (both read and write), however 8-bit write doesn't.

Using base address 0xA0000000 only 8-bit write at offests: 0x0, 0x1 and 0x8, 0x9 work. The cycle repeats every 16 bytes, writes at remaining offests are ignored (no BusFault but memory content is unchanged). I've attached sample program (C++) that zeroes entire memory, than it writes 0xAD to each memory byte. Memory content after the execution is shown on attached screenshot.

I also tried to replicate design from scratch with the same result.


Update: I've used IP Core for SDRAM from this repository: as a replacemnt for CoreSDR_AXI IP (and AHB-Lite to AXI conversion) and it worked (even with default paramters).

If someone else would be able to verify the result, then I'm going to report support case to Microsemi as (at least for now) that CoreSDR_AXI is broken

Antti Lukats


sorry for no quick answer - Microsemi IP core works too, but we are in backlog updating the reference designs, sorry.

and many many thank you for trying out and posting info about the success with the 3rd part SDRAM IP core, this is very good to know that it worked so easily!

ups, we have actually not verified byte access, we know that the SDRAM works but we have not done much testing ourself. I would still assume microsemi IP can also support byte accesses.



Any info on updating reference design?

Antti Lukats

Hi sorry no - we will update all SmartFusion2 designs to Libero 12.x - if there are still issues with external SDRAM we would then ask Microsemi support directly.

I did assume that the problem is/was solved by some nasty workarounds or at least fully working (with 11.x Libero)



I hoped that it was solved, however last week I hit some really weird issues (strange hardfaults, missing interrupts, reads of initialized memory that looked like uninitialized). Playing with parameters of DDR Bridge and cached seems to change the probability of crash so I suspect that memory controlled is the cause here.

Unfortunately CoreSDR_AXI (used by Microsemi by default) does not support byte access (it is written in its documentation) and I was unable to get CoreSDR_AHB to work.

Antti Lukats

so are you using the axiSDRAM ?

we had also some really bad issues, and had to-do something funky to get it properly working, and I think it did  work, and that design actually should be online, but already for ages.


I was trying various solutions.

To sum up:

  • Design that is linked on the SMF2000 page (it uses CoreSDR_AXI) - result is the same as in the first post (some bytes are not written).
  • Manually recreated design using default components (CoreSDR_AXI) - result is the same as provided design
  • CoreSDR_AHB but it was not writing anything at all (all reads came back as zeros)
  • 3rd party IP Core - seemed to work at the begining but that program started crashing in ways that doesn't make any sense

It would be great if someone else owning the board could verify the issue.