EDDP-EDPS Support

TE0950 Versal support on Vitis, how to proceed?

Started by jlei

Replies: 1
Views: 2,021

September 17, 2024, 10:18:27 AM
by M Kirberg

unable to boot TE0950 with prebuilt files

Started by eejlny

Replies: 1
Views: 2,856

August 20, 2024, 08:48:45 AM
by JH

TE0950 Power consumption / Heat dissipation

Started by dje666

Replies: 1
Views: 5,323

July 10, 2024, 07:57:56 AM
by M Kirberg

How to initialize the EDDP by BTN3

Started by Jason bourne

Replies: 34
Views: 30,968

February 01, 2023, 02:20:12 AM
by Jason bourne

How Xilinx_eddp_mode Change

Started by Jason bourne

Replies: 3
Views: 12,737

December 01, 2022, 01:54:12 PM
by Andrei Errapart

problem when run Vivado HLS example

Started by jinyu

Replies: 4
Views: 10,959

November 01, 2022, 06:15:18 AM
by Jason bourne

TE0802 SD boot fail

Started by dyne21

Replies: 3
Views: 12,259

August 26, 2022, 09:36:11 AM
by JH

Serial/UART not working on Linux with the SMF2000

Started by adrien220615

Replies: 0
Views: 11,751

June 15, 2022, 06:07:48 PM
by adrien220615

TEB0745 IO/Expander Addresses Issue

Started by AhmedShaaban

Replies: 4
Views: 12,293

March 02, 2022, 07:47:05 AM
by AhmedShaaban

TEF0008 - FPGA to Mezzanine Card (FMC) - Rate select issue

Started by georgian.andrei

Replies: 1
Views: 12,601

November 08, 2021, 05:05:36 PM
by Martin R.

PI Controller for Flux

Started by TY

Replies: 4
Views: 14,570

September 14, 2020, 05:18:08 PM
by TY

Data types of Kp and Ki parameters for PI Control

Started by TY

Replies: 4
Views: 13,792

September 03, 2020, 04:20:20 PM
by TY

Xilinx Zynq ZedBoard compatibility

Started by rfsweitzer

Replies: 1
Views: 12,831

September 03, 2020, 06:35:17 AM
by JH

Updating HW config for SDx

Started by Henry

Replies: 8
Views: 15,468

February 24, 2020, 07:43:57 AM
by ssysheldon1

PI Control in foc.cpp

Started by shivang1993

Replies: 22
Views: 23,025

August 06, 2019, 10:56:56 PM
by shivang1993

EDDP - ADC & PWM synchronization

Started by valahia

Replies: 4
Views: 14,295

June 12, 2019, 03:00:10 AM
by valahia

Change the value in argument registers

Started by shivang1993

Replies: 3
Views: 13,844

June 11, 2019, 11:23:42 AM
by Andrei Errapart

SDSoC project platform and Vivado design

Started by valahia

Replies: 4
Views: 14,122

June 06, 2019, 10:43:55 PM
by valahia

How to modify poles pairs parameters in the HLS reference design?

Started by jinyu

Replies: 1
Views: 21,579

June 07, 2018, 10:15:15 AM
by Oleksandr Kiyenko

After generate bitstream, What should do the next?

Started by jinyu

Replies: 4
Views: 10,731

April 12, 2018, 10:20:30 AM
by jinyu

invalid TCL command name "TE::hw_xxxx_xxx"

Started by jinyu

Replies: 2
Views: 9,894

April 10, 2018, 02:04:23 PM
by jinyu

The Design Fail to Meet the Timing Requirement

Started by jinyu

Replies: 14
Views: 18,099

April 10, 2018, 12:21:19 PM
by jinyu

Why this slice was not connected ?

Started by jinyu

Replies: 2
Views: 9,852

April 10, 2018, 12:16:35 PM
by jinyu

How to simulate the PWM IP Core in vivado

Started by jinyu

Replies: 2
Views: 10,595

April 10, 2018, 12:13:00 PM
by jinyu

Xilinx IIoT-EDDP SDSoC v2017.4 support

Started by ggaroia

Replies: 1
Views: 12,610

February 07, 2018, 12:32:06 PM
by JH